Design & implementation of high speed low power scan flip-flop
S Janwadkar, MT Kolte - 2016 IEEE International Conference …, 2016 - ieeexplore.ieee.org
Over the years, The semiconductor industry has made tremendously impressive
improvement in terms of density of very large-scale integrated (VLSI) circuits. Increasing …
improvement in terms of density of very large-scale integrated (VLSI) circuits. Increasing …
Reduction of testing power with pulsed scan flip-flop for scan based testing
DS Valibaba, S Sivanantham, PS Mallick… - 2011 International …, 2011 - ieeexplore.ieee.org
In this paper, a new scan flip-flop is proposed for low power testing. Different flip-flops
(Master-slave, hybrid, pulse triggered) are reviewed and evaluated their performance using …
(Master-slave, hybrid, pulse triggered) are reviewed and evaluated their performance using …
High Performance and Power-Aware Scan Flip-Flop Design
K Eedupuganti, NS Murty - 2017 IEEE international conference …, 2017 - ieeexplore.ieee.org
Every single manufactured chip must be tested for manufacturing defects, and today, it is
reported that 30% of the overall production cost is due to testing. Testing cost of a chip is …
reported that 30% of the overall production cost is due to testing. Testing cost of a chip is …
On minimization of test power through modified scan flip-flop
S Ahlawat, JT Tudu - … Symposium on VLSI Design and Test …, 2016 - ieeexplore.ieee.org
Power dissipation during scan testing of modern high complexity designs could be many
folds higher than the functional operation power, which is a well established observation …
folds higher than the functional operation power, which is a well established observation …
[PDF][PDF] A Modified Scan-D Flip-flop Design to Reduce Test Power.
SP Khatri, S Ganesan - 15th IEEE/TTTC International Test …, 2008 - people.engr.tamu.edu
Power consumption in scan based testing is high due to the toggling of the combinational
logic during the scan shift. In this paper, we present a modified Scan Flip-flop architecture …
logic during the scan shift. In this paper, we present a modified Scan Flip-flop architecture …
A power-effective scan architecture using scan flip-flops clustering and post-generation filling
Z Chen, D Xiang, B Yin - Proceedings of the 19th ACM Great Lakes …, 2009 - dl.acm.org
In this paper, we propose a novel way to save test power, using the DFT based technique as
basic method and post-generation filling as complementary. In this architecture, two …
basic method and post-generation filling as complementary. In this architecture, two …
A new scan flip flop design to eliminate performance penalty of scan
S Ahlawat, J Tudu, A Matrosova… - 2015 IEEE 24th Asian …, 2015 - ieeexplore.ieee.org
The demand for high performance system-on-chips (SoC) in communication and computing
has been growing continuously. To meet the performance goals, very aggressive circuit …
has been growing continuously. To meet the performance goals, very aggressive circuit …
A technique for low power testing of VLSI chips
R Jayagowri, KS Gurumurthy - 2012 International Conference …, 2012 - ieeexplore.ieee.org
Power consumption of a circuit is more in test mode than normal mode. The increased heat
due to excess power dissipation can open up reliability issue due to electro-migration. In …
due to excess power dissipation can open up reliability issue due to electro-migration. In …
Approximate Scan Flip-flop to Reduce Functional Path Delay and Power Consumption
LBR Konduru, V Lakshmi, JT Tudu - arXiv preprint arXiv:2212.12360, 2022 - arxiv.org
The scan-based testing has been widely used as a Design-for-Test (DfT) mechanism for
most recent designs. It has gained importance not only in manufacturing testing but also in …
most recent designs. It has gained importance not only in manufacturing testing but also in …
A bypassable scan flip-flop for low power testing with data retention capability
X Cao, H Jiao, EJ Marinissen - IEEE Transactions on Circuits …, 2021 - ieeexplore.ieee.org
The power consumption of modern highly complex chips during scan test is significantly
higher than the power consumed during functional mode. This leads to substantial heat …
higher than the power consumed during functional mode. This leads to substantial heat …