Stacked packaging using reconstituted wafers
KK Hu, SZ Zhao, RR Khan, P Vorenkamp… - US Patent …, 2016 - Google Patents
BACKGROUND Packaging for dies that include, for example, at least one integrated circuit
(IC), is continually trending towards reduced package size with increased package density …
(IC), is continually trending towards reduced package size with increased package density …
Stacked Packaging Using Reconstituted Wafers
KK Hu, SZ Zhao, RR Khan, P Vorenkamp… - US Patent App. 13 …, 2013 - Google Patents
BACKGROUND 0001 Packaging for dies that include, for example, at least one integrated
circuit (IC), is continually trending towards reduced package size with increased package …
circuit (IC), is continually trending towards reduced package size with increased package …
Flexibly-wrapped integrated circuit die
S Albers, M Skinner, HJ Barth, P Baumgartner… - US Patent …, 2016 - Google Patents
BACKGROUND As manufacturers attempt to reduce the size of electronic devices, they may
find ways to combine integrated circuit dies in order to make the electronics of the device …
find ways to combine integrated circuit dies in order to make the electronics of the device …
Packaging mechanisms for dies with different sizes of connectors
CH Chen, CS Chen, CW Hsiao - US Patent 9,646,894, 2017 - Google Patents
BACKGROUND Semiconductor devices are used in a variety of electronic applications, such
as personal computers, cell phones, digi tal cameras, and other electronic equipment, as …
as personal computers, cell phones, digi tal cameras, and other electronic equipment, as …
Heterogeneous Technology Integration
J Kim, EP Gousev, MM Nowak - US Patent App. 12/731,520, 2011 - Google Patents
BACKGROUND 0002 Integrated circuits can be designed using different technologies, for
example complementary metal oxide semi conductor (CMOS) technology, glass technology …
example complementary metal oxide semi conductor (CMOS) technology, glass technology …
Configuring a performance state of an integrated circuit die on wafer
J Emmert, M Rencher, C Evans - US Patent App. 10/847,258, 2005 - Google Patents
BACKGROUND 0001. A manufacturing process for an integrated circuit may include forming
a Set of integrated circuit dies on a wafer, cutting the integrated circuit dies from the wafer …
a Set of integrated circuit dies on a wafer, cutting the integrated circuit dies from the wafer …
Pad configurations for an electronic package assembly
S Sutardja, SM Liou, H Kao - US Patent 9,331,052, 2016 - Google Patents
BACKGROUND The background description provided herein is for the pur pose of generally
presenting the context of the disclosure. Work of the presently named inventors, to the extent …
presenting the context of the disclosure. Work of the presently named inventors, to the extent …
Pad configurations for an electronic package assembly
S Sutardja, SM Liou, H Kao - US Patent 8,860,193, 2014 - Google Patents
BACKGROUND The background description provided herein is for the pur pose of generally
presenting the context of the disclosure. Work of the presently named inventors, to the extent …
presenting the context of the disclosure. Work of the presently named inventors, to the extent …
Die backside wire bond technology for single or stacked die package
S Periaman, KC Ooi, BE Cheah, YH Chew - US Patent 8,198,716, 2012 - Google Patents
BACKGROUND The present disclosure generally relates to the field of electronics. More
particularly, an embodiment of the inven tion relates to die backside wire bond technology. A …
particularly, an embodiment of the inven tion relates to die backside wire bond technology. A …
Integrated circuit packaging configurations
SM Liou, A Wu - US Patent 8,884,419, 2014 - Google Patents
BACKGROUND The background description provided herein is for the pur pose of generally
presenting the context of the disclosure. Work of the presently named inventors, to the extent …
presenting the context of the disclosure. Work of the presently named inventors, to the extent …