Leakage control through fine-grained placement and sizing of sleep transistors
V Khandelwal, A Srivastava - IEEE transactions on computer …, 2007 - ieeexplore.ieee.org
Multithreshold CMOS (MTCMOS) technology has become a popular technique for standby
power reduction. Sleep transistor insertion in circuits is an effective application of MTCMOS …
power reduction. Sleep transistor insertion in circuits is an effective application of MTCMOS …
Fine-grained sleep transistor sizing algorithm for leakage power minimization
Power gating is one of the most effective ways to reduce leakage power. In this paper, we
introduce a new relationship among Maximum Instantaneous Current, IR drops and sleep …
introduce a new relationship among Maximum Instantaneous Current, IR drops and sleep …
Coarse-grain MTCMOS sleep transistor sizing using delay budgeting
E Pakbaznia, M Pedram - Proceedings of the conference on Design …, 2008 - dl.acm.org
Power gating is one of the most effective techniques in reducing the standby leakage current
of VLSI circuits. In this paper we introduce a new approach for sleep transistor sizing which …
of VLSI circuits. In this paper we introduce a new approach for sleep transistor sizing which …
Row-based power-gating: A novel sleep transistor insertion methodology for leakage power optimization in nanometer CMOS circuits
Leakage power has become a serious concern in nanometer CMOS technologies, and
power-gating has shown to offer a viable solution to the problem with a small penalty in …
power-gating has shown to offer a viable solution to the problem with a small penalty in …
Fast techniques for standby leakage reduction in MTCMOS circuits
Technology scaling causes subthreshold leakage currents to increase exponentially.
Therefore, effective leakage minimization techniques must be designed. In addition, for a …
Therefore, effective leakage minimization techniques must be designed. In addition, for a …
Post-layout leakage power minimization based on distributed sleep transistor insertion
This paper introduces a new approach to sub-threshold leakage power reduction in CMOS
circuits. Our technique is based on automatic insertion of sleep transistors for cutting sub …
circuits. Our technique is based on automatic insertion of sleep transistors for cutting sub …
Timing driven power gating
DS Chiou, SH Chen, SC Chang, C Yeh - Proceedings of the 43rd …, 2006 - dl.acm.org
Power Gating is effective for reducing leakage power. Previously, a Distributed Sleep
Transistor Network (DSTN) was proposed to reduce the sleep transistor area by connecting …
Transistor Network (DSTN) was proposed to reduce the sleep transistor area by connecting …
Timing-driven row-based power gating
In this paper we focus on leakage reduction through automatic insertion of sleep transistors
using a row-based granularity. In particular, we tackle here the two main issues involved in …
using a row-based granularity. In particular, we tackle here the two main issues involved in …
MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
J Kao, S Narendra, A Chandrakasan - Proceedings of the 35th annual …, 1998 - dl.acm.org
Multi-threshold CMOS is a popular circuit style that will provide high performance and low
power operation. Optimally sizing the gating sleep transistor to provide adequate …
power operation. Optimally sizing the gating sleep transistor to provide adequate …
Efficient computation of discharge current upper bounds for clustered sleep transistor sizing
A Sathanur, A Calimera, L Benini… - … , Automation & Test …, 2007 - ieeexplore.ieee.org
Sleep transistor insertion is a key step in low power design methodologies for nanometer
CMOS. In the clustered sleep transistor approach, a single sleep transistor is shared among …
CMOS. In the clustered sleep transistor approach, a single sleep transistor is shared among …