This paper introduces a novel method for automatically tuning the selection of compiler flags
to optimize the performance of software intended to run on embedded hardware platforms …

Generating instead of implementing variable design platforms is becoming increasingly
popular in the development of System on Chips. This shift also poses the challenge of rapid …

Modern compilers implement a large number of optimizations which all interact in complex
ways, and which all have a different impact on code quality, compilation time, code size …

Despite ceaseless efforts, extremely large and complex optimization space makes even the
state-of-the-art compilers fail in delivering the most performant setting that can fully utilize the …

There is an increasing need to bring machine learning to a wide diversity of hardware
devices. Current frameworks rely on vendor-specific operator libraries and optimize for a …

Performing Deep Neural Network (DNN) computation on hardware accelerators efficiently is
challenging. Existing DNN frameworks and compilers often treat the DNN operators in a …

Building an optimising compiler is a difficult and time consuming task which must be
repeated for each generation of a microprocessor. As the underlying microarchitecture …

Existing iterative compilation and machine learning-based optimization techniques have
been proven very successful in achieving better optimizations than the standard optimization …

Designing new microprocessors is a time consuming task. Architects rely on slow simulators
to evaluate performance and a significant proportion of the design space has to be explored …

We live in a new Cambrian Explosion of hardware devices. The end of conventional
processor scaling has driven research and industry practice to explore a new generation of …