A Bang-Bang Clock and Data Recovery (CDR) with adaptive loop gain strategy is
presented. The proposed strategy enhances CDR jitter performance even if jitter spectrum …

A loop gain adaptation technique is proposed, which optimizes the jitter tolerance (JTOL) of
a 28 Gb/s phase interpolator (PI)-based clock and data recovery (CDR) circuit implemented …

A digital clock and data recovery circuit (CDR) employs hybrid analog/digital phase
detection to achieve linear loop dynamics and to eliminate the nonlinearity and quantization …

A continuous-rate digital clock and data recovery (CDR) with automatic frequency
acquisition is presented. The proposed automatic frequency acquisition scheme …

A jitter-tolerance-enhanced 10 Gb/s clock and data recovery (CDR) circuit is presented. The
proposed architecture cascades 2 half-rate CDRs with different loop bandwidth to relax the …

This paper embeds a “phase-reset” scheme into a bang-bang clock and data recovery
(CDR) to periodically realign the clock phase to the data rising edge using a gated-VCO …

As we move to higher data rates, the performance of clock and data recovery (CDR) circuits
becomes increasingly important in maintaining low bit error rates (BER) in wireline links …

This paper presents a digital bang-bang phase-locked loop (DBPLL) that employs automatic
loop gain control and loop latency reduction techniques to enhance the jitter performance …

In this brief, a 1/10-rate bang-bang phase detector (BBPD) using a single edge-tracking
clock and a phase interpolator (PI)-based clock and data recovery (CDR) circuit with the …

We demonstrate a clock and data recovery (CDR) circuit having a new type of a multi-level
bang-bang phase detector (ML-BBPD). The gain characteristics of our ML-BBPD can be …