A PFD and Charge Pump switching circuit to optimize the output phase noise of the PLL in 0.13-µm CMOS
MK Hati, TK Bhattacharyya - 2015 International Conference on …, 2015 - ieeexplore.ieee.org
This paper presents the design of a novel Phase Frequency Detector (PFD) and Charge
Pump (CP) switching circuits for the frequency synthesizer in phase-locked loop (PLL). Our …
Pump (CP) switching circuits for the frequency synthesizer in phase-locked loop (PLL). Our …
CMOS phase frequency detector and charge pump for multi-standard frequency synthesizer
L Tang, X Fan, Z Hua - 2015 IEEE International Conference on …, 2015 - ieeexplore.ieee.org
An improved phase frequency detector (PFD) and a novel charge pump (CP) for phase
locked loop (PLL) applications are presented. The mechanisms for widening the phase error …
locked loop (PLL) applications are presented. The mechanisms for widening the phase error …
Design of a low power charge pump circuit for phase-locked loops
H Xu, Z Li - 2012 4th International High Speed Intelligent …, 2012 - ieeexplore.ieee.org
In this paper, the design of a charge pump circuit suitable for lower power PLL-based
frequency synthesizer is presented. The charge pump circuit was designed in 0.18 μm …
frequency synthesizer is presented. The charge pump circuit was designed in 0.18 μm …
Design of low power and high speed phase detector
High-speed phase frequency detector (PFD) is one of the key module for high-frequency
phase locked loop (PLL) systems. The performance of PLL depends on the operation of …
phase locked loop (PLL) systems. The performance of PLL depends on the operation of …
Power optimized PLL implementation in 180nm CMOS technology
P Sreehari, P Devulapalli, D Kewale… - … Symposium on VLSI …, 2014 - ieeexplore.ieee.org
This paper describes the design of power optimized phase locked loop for frequency
synthesis, Clock and Data recovery, carrier synchronization and many more communication …
synthesis, Clock and Data recovery, carrier synchronization and many more communication …
A high speed, low jitter and fast acquisition CMOS phase frequency detector for charge pump PLL
MK Hati, TK Bhattacharyya - Progress in VLSI Design and Test: 16th …, 2012 - Springer
This paper presents the different design schemes of the phase frequency detector (PFD) and
compares with the output simulation results. The circuits that have been considered are the …
compares with the output simulation results. The circuits that have been considered are the …
Reduction of current mismatch in PLL charge pump
HMS Fazeel, L Raghavan… - 2009 IEEE Computer …, 2009 - ieeexplore.ieee.org
Low static phase offset is desired in Phase Locked Loops (PLL) employed in high speed I/O
interfaces and frequency synthesizers. In this work, non idealities in phase frequency …
interfaces and frequency synthesizers. In this work, non idealities in phase frequency …
A phase-frequency detector and a charge pump design for PLL applications
S Milicevic, L MacEachern - 2008 IEEE International …, 2008 - ieeexplore.ieee.org
An improved phase frequency detector (PFD) and a novel charge pump (CP) for phase
locked loop (PLL) applications are presented. Implemented in a CMOS 0.13 μm technology …
locked loop (PLL) applications are presented. Implemented in a CMOS 0.13 μm technology …
A 2.4-GHz reference doubled fractional-N PLL with dual phase detector in 0.13-μm CMOS
W Lee, SH Cho - … of 2010 IEEE International Symposium on …, 2010 - ieeexplore.ieee.org
This paper presents a low noise fractional-N PLL that employs the reference multiplication
technique. In order to reduce the noise from ΔΣ modulator (DSM) and charge-pump (CP) …
technique. In order to reduce the noise from ΔΣ modulator (DSM) and charge-pump (CP) …
Design of a CMOS PFD-CP module for a PLL
NK Anushkannan, H Mangalam - Sadhana, 2015 - Springer
This paper introduces a modified design of Phase frequency detector (PFD) with reduced
dead zone and improved charge pump (CP) with reduced current mismatch for a Phase …
dead zone and improved charge pump (CP) with reduced current mismatch for a Phase …