Power dissipation in digital systems may be significantly high during scan testing where a
large portion of power is consumed in the combinational part. This paper presents a new …

Power consumption during testing is becoming a primary concern. In this paper, an
adjustable clock scan structure is presented. It can significantly reduce the peak power …

Power consumption in scan based testing is high due to the toggling of the combinational
logic during the scan shift. In this paper, we present a modified Scan Flip-flop architecture …

Test power is now a big concern in large core-based systems. In this paper, we present a
general approach for minimizing power consumption during test of integrated circuits or …

Scanning of test vectors during testing causes unnecessary and excessive switching in the
combinational circuit compared to that in the normal operation. In this paper, we propose a …

Latest VLSI circuits face the problem of power dissipation not only in design phase but also
during testing phase. Power dissipation during testing may be increased up to three times …

Since VLSI technology has become ubiquitous in today's world, this field is a prime
candidate for power reduction. Tremendous growth in chip density and reduction in …

Power dissipation during scan testing of modern high complexity designs could be many
folds higher than the functional operation power, which is a well established observation …

It is seen that power dissipation during test mode is quite high compared to that during the
functional mode of operation of a digital circuit. This may lead to damage of certain chips …

As the serial scan design has been one of the most popular methods in VLSI circuit test,
power consumption during test increases significantly because of its inherent shift mode. To …