Every single manufactured chip must be tested for manufacturing defects, and today, it is
reported that 30% of the overall production cost is due to testing. Testing cost of a chip is …

Time, power, and data volume are among some of the most challenging issues for testing
System-on-Chip (Soc.) and have not been fully resolved, even if a scan-based technique is …

Circuit switching activity during scan test is high and results in high average and
instantaneous power consumption, which is becoming a concern for scan-based …

We present a novel scan architecture for simultaneously reducing test application time and
test power (both average and peak power). Unlike previous works where the scan chain is …

In this paper, we propose a novel way to save test power, using the DFT based technique as
basic method and post-generation filling as complementary. In this architecture, two …

This paper presents a novel toggle-masking technique that eliminates the switching activity
in a circuit under test (CUT) during the scan-shifting in a test-per-scan test. Conventional …

The testing power is the biggest concern in modern VLSI chip testing as the testing power is
very greater than the functional power which affects the reliability of the chip. In this paper …

In recent years, with fast growth of mobile communication and portable computing systems,
design for low power has become the challenge in the field of Digital VLSI design. The main …

Power dissipated during test application is substantially higher than power dissipated during
functional operation which can decrease the reliability and lead to yield loss. This paper …