Low-power scan design using first-level supply gating
S Bhunia, H Mahmoodi, D Ghosh… - … Transactions on Very …, 2005 - ieeexplore.ieee.org
Reduction in test power is important to improve battery lifetime in portable electronic devices
employing periodic self-test, to increase reliability of testing, and to reduce test cost. In scan …
employing periodic self-test, to increase reliability of testing, and to reduce test cost. In scan …
An efficient pulse flip-flop based launch-on-shift scan cell
At-speed testing is essential for VLSI ICs implemented in nanometer technologies, operating
at high clock speeds. Traditional scan based methodologies can be used for at-speed …
at high clock speeds. Traditional scan based methodologies can be used for at-speed …
[PDF][PDF] Design and Implementation of Area and Power Optimised Novel ScanFlop
R Jayagowri, KS Gurumurthy - International Journal of VLSI design & …, 2011 - Citeseer
The power consumption of IC during test mode is higher than its normal mode. This brings
the power as one of the major design constraints for today's low power design technologies …
the power as one of the major design constraints for today's low power design technologies …
Algorithm for low power combinational circuit testing
K Paramasivam, K Gunavathi… - 2004 IEEE Region 10 …, 2004 - ieeexplore.ieee.org
Power dissipation during testing of VLSI circuits is major concern due to the switching
activity of the circuit under test. In this paper, a novel method is presented, that aims at …
activity of the circuit under test. In this paper, a novel method is presented, that aims at …
VLSI implementation of low power scan based testing
S Ukey, S Rathkanthiwar… - … on Communication and …, 2016 - ieeexplore.ieee.org
Power consumption in test becomes a higher barrier for consideration in test of any
combinational circuit is high during test mode as in its normal mode of functioning as …
combinational circuit is high during test mode as in its normal mode of functioning as …
Low power testing using re-configurable Johnson counter and scalable SIC counter
P Margade - 2015 International Conference on …, 2015 - ieeexplore.ieee.org
This paper deals with a low power approach to generate test pattern for Built In Self Test.
Test pattern generated using LFSR has high switching activity and thus a single input …
Test pattern generated using LFSR has high switching activity and thus a single input …
Elimination of output gating performance overhead for critical paths in scan test
AK Suhag, S Ahlawat… - … Journal of Circuits …, 2013 - inderscienceonline.com
Excessive switching activity in test mode results in higher power dissipation than normal
mode of operation and becoming a serious issue, in order to avoid reliability problems …
mode of operation and becoming a serious issue, in order to avoid reliability problems …
Low power testing of VLSI circuits: Problems and solutions
P Girard - … IEEE 2000 First International Symposium on Quality …, 2000 - ieeexplore.ieee.org
Power and energy consumption of digital systems may increase significantly during testing.
This extra power consumption due to test application may give rise to severe hazards to the …
This extra power consumption due to test application may give rise to severe hazards to the …
Output gating performance overhead elimination for scan test
AK Suhag, S Ahlawat, V Shrivastava… - International Journal of …, 2015 - Taylor & Francis
Switching activity is much higher in test mode as compared to normal mode of operation
which causes higher power dissipation, and this leads to several reliability issues. Output …
which causes higher power dissipation, and this leads to several reliability issues. Output …