Modern IC design and manufacturing techniques are growing such that the transistor count
on a single chip escalates exponentially with complex Embedded and DSP cores in it …

The testing power is the biggest concern in modern VLSI chip testing which affects the
reliability of the chip. The testing power is very greater than the functional power because …

A new simple built-in-self-test (BIST) structure for low power testing is presented in this
paper. The principle of the proposed method is to reconstruct the LFSR circuit to reduce the …

Power consumption has become a crucial concern in Built In Self Test (BIST) due to the
switching activity in the circuit under test (CUT). In this paper we present a novel method …

A scan-chain architecture that utilizes the existence of don't care bits (X-bits) in test cubes to
provide test application time reduction at reduced power consumption is proposed …

This paper presents a low-power test scheme by using random single input change (RSIC)
technique. By adding simple control logic on original linear feedback shift register (LFSR) …

The paper presents a novel technique for power minimization during test application in
sequential circuits using multiple scan chains. The technique is based on a new design for …

This paper addresses the issue of blocking pattern selection to reduce both leakage and
peak power consumption during circuit testing using scan-based approach. The blocking …

The temperature of a block (a region in the chip) depends on both heat generation (caused
by power consumption) and heat dissipation among neighbors. Power aware test solutions …