Reducing Power During Manufacturing Test Using Different Architectures
Y Sun - 2021 - scholar.smu.edu
Power during manufacturing test can be several times higher than power consumption in
functional mode. Excessive power during test can cause IR drop, over-heating, and early …
functional mode. Excessive power during test can cause IR drop, over-heating, and early …
An efficient algorithm to reduce test power consumption by scan cell and scan vector reordering
KVA Reddy, S Chattopadahyay - Proceedings of the IEEE …, 2004 - ieeexplore.ieee.org
It is well known that excessive switching activity during scan testing can cause average
power and peak power dissipation during test to be much higher than the normal mode …
power and peak power dissipation during test to be much higher than the normal mode …
[PDF][PDF] Scan latch partitioning into multiple scan chains for power minimization in full scan sequential circuits
N Nicolici, BM Al-Hashimi - Proceedings of the conference on Design …, 2000 - dl.acm.org
Power dissipated during test application is substantially higher than power dissipated during
functional operation [22] which can decrease the reliability and lead to yield loss. This paper …
functional operation [22] which can decrease the reliability and lead to yield loss. This paper …
An improved low transition test pattern generator for low power applications
G Vellingiri, R Jayabalan - Design Automation for Embedded Systems, 2017 - Springer
VLSI circuits are perceived to dissipate extra power during testing when compared with that
of the normal function. Drastic heat may reduce circuit consistency, shoot up package cost …
of the normal function. Drastic heat may reduce circuit consistency, shoot up package cost …
Jump scan: A DFT technique for low power testing
MH Chiu, JCM Li - 23rd IEEE VLSI Test Symposium (VTS'05), 2005 - ieeexplore.ieee.org
This paper presents a Jump scan technique (or J-scan) for low power testing. The J-scan
shifts two bits of scan data per clock cycle so the scan clock frequency is halved without …
shifts two bits of scan data per clock cycle so the scan clock frequency is halved without …
[PDF][PDF] A novel random access scan flip-flop design
AS Mudlapur, VD Agrawal, AD Singh - Proc. 9th VLSI Design and …, 2005 - eng.auburn.edu
Serial scan design causes unnecessary switching activity during testing causing enormous
power dissipation. The test time increases enormously with the increase in number of flip …
power dissipation. The test time increases enormously with the increase in number of flip …
Low Power High Fault Coverage Test Techniques for Digital VLSI Circuits
A Abu Issa - 2009 - fada.birzeit.edu
Testing of digital VLSI circuits entails m VLSI CIRCUITS any challenges as a consequence
of rapid emiconductor manufacturing technology and the unprecedented levels of BIST. The …
of rapid emiconductor manufacturing technology and the unprecedented levels of BIST. The …