Testing of digital VLSI circuits entails m VLSI CIRCUITS any challenges as a consequence of rapid emiconductor manufacturing technology and the unprecedented levels of BIST. The …
Y Bonhomme, P Girard, L Guiller… - … 10th Asian Test …, 2001 - ieeexplore.ieee.org
Test power is now a big concern in large system-on-chip designs. In this paper, we present a novel approach for minimizing power consumption during scan testing of integrated circuits …
W Wei, H Yinhe, L Xiaowei… - Chinese Journal of …, 2009 - ieeexplore.ieee.org
Low-power design has become a challenge of test. We propose an effective low-power scan architecture named PowerSluice to minimize power consumption during scan test, which is …
I Pomeranz - IEEE Transactions on Computer-Aided Design of …, 2011 - ieeexplore.ieee.org
The power dissipation during the application of scan-based tests can be significantly higher than during functional operation. An exception is the second, fast functional capture cycles of …
S Kajihara, K Ishida, K Miyase - IEICE TRANSACTIONS on …, 2002 - search.ieice.org
This paper presents a test vector modification method for reducing average power dissipation during test application for a full-scan circuit. The method first identifies a set of …
R Schuchard, D Weiss - 1987 IEEE International Solid-State …, 1987 - ieeexplore.ieee.org
On-chip test support circuitry has been developed for a 32b multichip VLSI computer. The test support consists of a test PLA and a 45MHz diagnostic interface port that multiplexes up …
TC Huang, KJ Lee - Electronics Letters, 2001 - IET
A multiphase clocking technique is presented for reducing the test power for scan-based circuits. A novel scan cell design called the token scan cell is developed, which combines a …