Power reduction through X-filling of transition fault test vectors for LOS testing
Launch-Off-Capture (LOC) and Launch-Off-Shift (LOS) are the two main test schemes for at-
speed scan delay testing. In [1, 2], authors proposed a comparison between LOC and LOS …
speed scan delay testing. In [1, 2], authors proposed a comparison between LOC and LOS …
Low Power High Fault Coverage Test Techniques for Digital VLSI Circuits
A Abu Issa - 2009 - fada.birzeit.edu
Testing of digital VLSI circuits entails m VLSI CIRCUITS any challenges as a consequence
of rapid emiconductor manufacturing technology and the unprecedented levels of BIST. The …
of rapid emiconductor manufacturing technology and the unprecedented levels of BIST. The …
A gated clock scheme for low power scan testing of logic ICs or embedded cores
Y Bonhomme, P Girard, L Guiller… - … 10th Asian Test …, 2001 - ieeexplore.ieee.org
Test power is now a big concern in large system-on-chip designs. In this paper, we present a
novel approach for minimizing power consumption during scan testing of integrated circuits …
novel approach for minimizing power consumption during scan testing of integrated circuits …
Co-optimization of dynamic/static test power in scan test
Low-power design has become a challenge of test. We propose an effective low-power scan
architecture named PowerSluice to minimize power consumption during scan test, which is …
architecture named PowerSluice to minimize power consumption during scan test, which is …
Scan shift power of functional broadside tests
I Pomeranz - IEEE Transactions on Computer-Aided Design of …, 2011 - ieeexplore.ieee.org
The power dissipation during the application of scan-based tests can be significantly higher
than during functional operation. An exception is the second, fast functional capture cycles of …
than during functional operation. An exception is the second, fast functional capture cycles of …
Average power reduction in scan testing by test vector modification
S Kajihara, K Ishida, K Miyase - IEICE TRANSACTIONS on …, 2002 - search.ieice.org
This paper presents a test vector modification method for reducing average power
dissipation during test application for a full-scan circuit. The method first identifies a set of …
dissipation during test application for a full-scan circuit. The method first identifies a set of …
Scan path testing of a multichip computer
R Schuchard, D Weiss - 1987 IEEE International Solid-State …, 1987 - ieeexplore.ieee.org
On-chip test support circuitry has been developed for a 32b multichip VLSI computer. The
test support consists of a test PLA and a 45MHz diagnostic interface port that multiplexes up …
test support consists of a test PLA and a 45MHz diagnostic interface port that multiplexes up …
Token scan cell for low power testing
TC Huang, KJ Lee - Electronics Letters, 2001 - IET
A multiphase clocking technique is presented for reducing the test power for scan-based
circuits. A novel scan cell design called the token scan cell is developed, which combines a …
circuits. A novel scan cell design called the token scan cell is developed, which combines a …