Loop retiming has been extensively studied to maximize instruction-level parallelism (ILP) of
multiple function units by rearranging the dependence delays in a uniform loop. Recently …

The new emerging non-volatile memory technology of Spin Torque Transfer RAM (STT-
RAM) has been proposed as a replacement for SRAM based cache. Recently its commercial …

Recently hybrid cache architecture consisting of both spin-transfer torque RAM (STT-RAM)
and SRAM has been proposed for energy efficiency. In hybrid caches, migration-based …

In this paper, we focus on a very long instruction word (VLIW) processor design that “shares”
its cache blocks when switching to different performance modes to alleviate the …

Last Level Caches (LLCs) play a critical role in reducing the number of costly off-chip
memory accesses. Hence, there is a demand to make the LLCs larger to meet the …

In hybrid cache architecture consisting of both STT-RAM and SRAM, migration based
techniques have been proposed. The migration technique dynamically moves write …

Within the ever-important memory hierarchy, little research is devoted to Memory
Management Unit (MMU) caches, implemented in modern processors to accelerate …

As capacity and complexity of on-chip cache memory hierarchy increases, the service cost to
the critical loads from last level cache (LLC), which are frequently repeated, has become a …

Memory speed has become a major performance bottleneck as more and more cores are
integrated on a multi-core chip. The widening latency gap between high speed cores and …

The Memory Management Unit (MMU) in modern processors now includes a Translation
Lookaside Buffer (TLB) that caches recently-used Page-Table Entries (PTEs), and prevents …