Reduced Z-datapath CORDIC rotator

K Maharatna, K El-Shabrawy… - 2008 IEEE International …, 2008 - ieeexplore.ieee.org
In this article we propose a novel scheme based on virtually scaling-free COordinate
Rotation DIgital Computer (CORDIC) algorithm to design a hardware efficient CORDIC …

CORDIC processor with carry-save architecture

R Kunemund, H Soldner… - ESSCIRC'90: Sixteenth …, 1990 - ieeexplore.ieee.org
A CORDIC processor for vector rotations using a carry-save architecture has been
developed and realized. The CORDIC algorithm is based on an iteration, directed by the …

Implementation of floating-point CORDIC rotation and vectoring based on look up tables and multipliers

SF Hsiao, CS Wen, HM Lee - 2010 International Symposium on …, 2010 - ieeexplore.ieee.org
A unified design is presented that can execute floating-point CORDIC operations in both
rotation and vectoring modes with significantly reduced computation latency. Unlike …

GH CORDIC-Based Architecture for Computing th Root of Single-Precision Floating-Point Number

Y Wang, Y Luo, Z Wang, Q Shen… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
This article presents hardware implementation for computing arbitrary roots of a single-
precision floating-point number. The proposed architecture is based on Generalized …

Design of high-throughput fixed-point complex reciprocal/square-root unit

D Wang, MD Ercegovac… - IEEE Transactions on …, 2010 - ieeexplore.ieee.org
Complex reciprocal and square-root operations are used in many digital signal processing
(DSP) and numerical computations. In particular, high-throughput fixed-point …

Ultralow-Latency VLSI Architecture Based on a Linear Approximation Method for Computing Nth Roots of Floating-Point Numbers

F Lyu, X Xu, Y Wang, Y Luo, Y Wang… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
State-of-the-art approaches that perform root computations based on the COordinate
Rotation Digital Computer (CORDIC) algorithm suffer from high latency in performing …

Low-power floating-point adaptive-CORDIC-based FFT twiddle factor on 65-nm silicon-on-thin-BOX (SOTB) with back-gate bias

TT Hoang, XT Nguyen, DH Le… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
In this brief, a silicon-on-thin-BOX (SOTB) implementation of single-precision floating-point
fast-Fourier-transform (FFT) twiddle factor (TF) is presented. The architecture of the …

FPGA Implementation of Polynomial Curve Fitting Approximation for Sine and Cosine Generator

RK Yousif, IA Hashim, BH Abd - 2022 5th International …, 2022 - ieeexplore.ieee.org
This paper is studying the trigonometric functions, such as sine and cosine, which play an
essential role in navigation, communication, and other modern digital signal processing …

A low-latency power series approximate computing and architecture for co-calculation of division and square root

D Tian, N Yu, M Xie, J Tang, Z Feng… - … on Circuits and …, 2024 - ieeexplore.ieee.org
The calculation of division and square root is widely used in edge computing related to
image processing, clustering, recognition, and reconstruction, among others. Their common …

A novel approximation methodology and its efficient vlsi implementation for the sigmoid function

Z Qin, Y Qiu, H Sun, Z Lu, Z Wang… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
In this brief, a novel approximation method and its optimized hardware implementation are
proposed for the sigmoid function used in Deep Neural Networks (DNNs). Based on …