Custom floating-point unit generation for embedded systems

YJ Chong, S Parameswaran - IEEE Transactions on Computer …, 2009 - ieeexplore.ieee.org
While application-specific instruction-set processors (ASIPs) have allowed designers to
create processors with custom instructions to target specific applications, floating-point (FP) …

Research and Hardware Implementation of a Reduced-Latency Quadruple-Precision Floating-Point Arctangent Algorithm

C He, B Yan, S Xu, Y Zhang, Z Wang, M Wang - Electronics, 2023 - mdpi.com
In the field of digital signal processing, such as in navigation and radar, a significant number
of high-precision arctangent function calculations are required. Lookup tables, polynomial …

A 500-MS/s 8.4-ps Double-Edge Successive Approximation TDC in 65 nm CMOS

R Siddiqui, F Yuan, Y Zhou - 2019 IEEE 62nd International …, 2019 - ieeexplore.ieee.org
This paper presents an 8.4 ps 500 MS/s 4-bit successive approximation register time-to-
digital converter (SAR-TDC). The TDC utilizes both the rising and falling edges of the cyclic …

Hybrid architecture design for calculating variable-length Fourier transform

SC Lai, WH Juang, YS Lee, SH Chen… - … on Circuits and …, 2015 - ieeexplore.ieee.org
This brief presents a hybrid structure to effectively compute the variable-length Fourier
transform by employing the recursive and radix-2 2 fast algorithm. After applying a hardware …

FPGA and ASIC square root designs for high performance and power efficiency

S Suresh, SF Beldianu… - 2013 IEEE 24th …, 2013 - ieeexplore.ieee.org
Floating-point square root is a fundamental operation in signal processing and various HPC
applications. Since this is an expensive operation in resource and energy consumption, its …

A high performance floating-point special function unit using constrained piecewise quadratic approximation

D De Caro, N Petra, AGM Strollo - 2008 IEEE International …, 2008 - ieeexplore.ieee.org
A special function unit, able to compute square root, reciprocal square root, logarithm and
exponential functions is presented in this paper. The system supports single precision IEEE …

A novel area-power efficient design for approximated small-point FFT architecture

X Han, J Chen, B Qin… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
Fast Fourier transform (FFT) is an essential algorithm in digital signal processing and
advanced mobile communications. With the continuous development of modern technology …

Design of high hardware efficiency approximate floating-point FFT processor

C Yan, X Zhao, T Zhang, J Ge… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
The Fast Fourier Transformation (FFT), as a high-efficiency algorithm of the Discrete Fourier
Transform (DFT), is widely used in Digital Signal Processing (DSP), wireless communication …

Exploring the combination of number of bits and number of iterations for a power-efficient fixed-point CORDIC implementation

AN Sapper, L Soares, E Costa… - 2017 24th IEEE …, 2017 - ieeexplore.ieee.org
This work explores approximation in CORDIC architectures for CMOS ASIC implementation.
Coarse grain reduction in the number of iterations and bit-width are systematically evaluated …

A Fast Algorithm Based on SRFFT for Length DFTs

W Zheng, K Li, K Li - … Transactions on Circuits and Systems II …, 2014 - ieeexplore.ieee.org
In this brief, we present a fast algorithm for computing length-q× 2 m discrete Fourier
transforms (DFT). The algorithm divides a DFT of size-N= q× 2 m decimation in frequency …