Reliable weighted globally congestion aware routing for network on chip

HC Touati, F Boutekkouk - … Journal of Embedded and Real-Time …, 2020 - igi-global.com
With the ability to incorporate hundreds of communicating cores on a single chip, thanks to
the continuous shrinkage in sizes, communication became of the utmost importance …

Design of fully adaptive routing for partially interconnected cross-link mesh topology for Network on Chip

R Mahar, S Choudhary, J Khichar - … Conference on Intelligent …, 2017 - ieeexplore.ieee.org
In this paper, we present a new fully adaptive routing algorithm for partially interconnected
cross-link mesh topology for NoC named as partially interconnected fully adaptive routing …

Review, analysis, and implementation of path selection strategies for 2D NoCS

R Singh, MK Bohra, P Hemrajani, A Kalla… - IEEE …, 2022 - ieeexplore.ieee.org
Recent advances in very-large-scale integration (VLSI) technologies have offered the
capability of integrating thousands of processing elements onto a single silicon microchip …

Reliable congestion-aware path prediction mechanism in 2D NoCs based on EFuNN

M Rezaei-Ravari, V Sattari-Naeini - The Journal of Supercomputing, 2018 - Springer
The efficiency of networks-on-chip (NoC) is affected by related routing algorithms. This
paper aims to develop a reliable routing mechanism in 2D mesh-based NoCs based on …

Novel metric for load balance and congestion reducing in network on-chip

A Aroui, P Boulet, K Benhaoua, AK Singh - … Computing: Practice and …, 2020 - scpe.org
Abstract The Network-on-Chip (NoC) is an alternative pattern that is considered as an
emerging technology for distributed embedded systems. The traditional use of multi-cores in …

A novel routing algorithm for on-chip communication in NoC on diametrical 2D mesh interconnection architecture

P Ghosal, TS Das - Advances in Computing and Information Technology …, 2013 - Springer
To meet the design productivity, scalability and signal integrity challenges of next-generation
system designs, a structured and scalable interconnection architecture, network on chip …

[PDF][PDF] Mesh topology of NoC architecture using source routing algorithm

VV Ingle, MA Gaikwad - Int J Eng Adv Technol (IJEAT), 2013 - Citeseer
NoC ie Network–on-Chip is one of today's emerging technology which has spread very fast
to meet today's need of fast communication. Few years back the communication was based …

GLB—Efficient Global Load Balancing method for moderating congestion in on-chip networks

M Daneshtalab, M Ebrahimi… - … International Workshop on …, 2012 - ieeexplore.ieee.org
Network Congestion can limit the performance of NoC due to increased transmission latency
and power consumption. In this paper, to reduce the network congestion, we present an …

A low-cost and latency bypass channel-based on-chip network

A Fadakar Noghondar, M Reshadi - The Journal of Supercomputing, 2015 - Springer
The number of cores on the chip increases rapidly; therefore, scalability is the most
important design choice. Mesh-based Networks-on-Chip (NoC) are the most widely used …

Congestion-aware routing algorithm for NoC using data packets

A Khurshid, MAJ Sethi, R Ullah… - Wireless …, 2021 - search.proquest.com
Abstract Network on Chip (NoC) is a communication framework for the Multiprocessor
System on Chip (MPSoC). It is a router-based communication system. In NoC architecture …