A VCO with high supply noise rejection and its application to PLL frequency synthesizer

T Sun, C Hui, Y Wang - IEEE International Symposium on …, 2005 - ieeexplore.ieee.org
A CMOS voltage-controlled oscillator (VCO) with high supply noise rejection is designed,
and its application to a phase-locked loop (PLL) frequency synthesizer is also presented. In …

An integrated low-noise CMOS PLL frequency synthesis

C Zhang, Y Li, H Chen, H Zhang - WCC 2000-ICSP 2000. 2000 …, 2000 - ieeexplore.ieee.org
A fully monolithic prototype frequency synthesis based on a phase-locked loop (PLL) is
described. To overcome the affections of noise, all the circuits of the synthesizer use a …

[PDF][PDF] Design of A 2GHz Low Phase Noise LC VCO

L Peiming, H Shizhen, S Lianyi, C Run - Proceedings of the International …, 2009 - iaeng.org
A design of a integrated LC-VCO which is used in the phase-locked loop frequency
synthesizer is presented. We reduce the phase noise effectively presupposes the tuning …

A 5 GHz fast-switching CMOS frequency synthesizer

X Yang, T Wu, J McMacken - 2002 IEEE Radio Frequency …, 2002 - ieeexplore.ieee.org
A 5 GHz PLL-based frequency synthesizer for wireless LAN applications is presented in this
paper. The proposed PLL is designed using 0.25/spl mu/m CMOS technology with 3.3 V …

A low noise CMOS wideband PLL with a new AAC LC-VCO

X Wu, W Sun, Z Chen, L Shi - 2005 6th International …, 2005 - ieeexplore.ieee.org
This paper presents a wideband CMOS PLL frequency synthesizer with a new AAC (auto-
amplitude control) VCO in 0.35 mum CMOS process. To get wideband VCO frequency …

Design and modelling of a low phase noise PLL frequency synthesizer

X He, W Kong, R Newcomb… - 2006 8th International …, 2006 - ieeexplore.ieee.org
This paper focuses on the low VCO sensitivity gain design, and modeling of a low phase
noise 2.4 GHz PLL frequency synthesizer. Tuning switch array is used in the LC tank to …

A smart frequency presetting technique for fast lock-in LC-PLL frequency synthesizer

X Yan, X Kuang, N Wu - 2009 IEEE International Symposium …, 2009 - ieeexplore.ieee.org
This paper proposes a smart frequency presetting technique for fast lock-in LC-PLL
frequency synthesizer. The technique accurately presets the frequency of VCO with small …

A 1.0 V GHz range 0.13/spl mu/m CMOS frequency synthesizer

L Sun, D Nelson - Proceedings of the IEEE 2001 Custom …, 2001 - ieeexplore.ieee.org
A 0.13/spl mu/m CMOS user programmable PLL frequency synthesizer is designed to
operate at low voltage (1.0-1.8 V) and cover a wide range of operating frequencies for …

A low jitter 5.3-GHz 0.18-/spl mu/m CMOS PLL based frequency synthesizer

S Ali, F Jain - 2002 IEEE Radio Frequency Integrated Circuits …, 2002 - ieeexplore.ieee.org
A 5.3-GHz CMOS phase locked loop (PLL) based frequency synthesizer is reported. The
PLL operates as an integer-N frequency synthesizer using a ring-type voltage controlled …

Low-power 2.4 GHz CMOS frequency synthesizer with differentially controlled MOS varactors

S Shin, K Lee, SM Kang - 2006 IEEE International Symposium …, 2006 - ieeexplore.ieee.org
A fully-differential quadrature PLL with common-mode noise immunity has been developed
by using a differentially controlled quadrature-VCO (Q-VCO) along with a differential charge …