Review, analysis, and implementation of path selection strategies for 2D NoCS

R Singh, MK Bohra, P Hemrajani, A Kalla… - IEEE …, 2022 - ieeexplore.ieee.org
Recent advances in very-large-scale integration (VLSI) technologies have offered the
capability of integrating thousands of processing elements onto a single silicon microchip …

Reducing bypass‐based network‐on‐chip latency using priority mechanism

AF Noghondar, M Reshadi… - IET Computers & Digital …, 2018 - Wiley Online Library
In the movement from a multi‐core to a many‐core era, cores count on the chip increases
quickly thus interconnect plays a large role in achieving the desired performance. Network …

Low‐cost regional‐based congestion‐aware routing algorithm for 2D mesh NoC

S Vazifedunn, A Reza… - International Journal of …, 2023 - Wiley Online Library
Given the advantages of network‐on‐chips (NoCs), they are rapidly improving to replace
other forms of System‐on‐Chip (SoC) designs. Although various factors improve the NoC's …

Implementation and evaluation of a congestion aware routing algorithm for networks-on-chip

LP Tedesco, T Rosa, F Clermidy, N Calazans… - Proceedings of the 23rd …, 2010 - dl.acm.org
The major part of the state of art routing proposals have a limited view of the NoC
congestion, since each router takes decisions based on few neighbors' status. Such local …

ParRouting: An efficient area partition-based congestion-aware routing algorithm for NoCs

J Fang, D Zhang, X Li - Micromachines, 2020 - mdpi.com
Routing algorithms is a key factor that determines the performance of NoC (Networks-on-
Chip) systems. Regional congestion awareness routing algorithms have shown great …

Design and implementation of congestion aware router for network-on-chip

MT Balakrishnan, TG Venkatesh, AV Bhaskar - Integration, 2023 - Elsevier
Abstract Network-on-Chip (NoC) is the state of the art on-chip interconnection network for
packet based communication. NoCs can offer low packet latency, high bandwidth, high …

Local congestion avoidance in network-on-chip

M Tang, X Lin, M Palesi - IEEE Transactions on Parallel and …, 2015 - ieeexplore.ieee.org
Network-on-Chip (NoC) has been made the communication infrastructure for many-core
architecture. NoC are subject to congestion, which is claimed to be avoided by many …

A hotspot-pattern-aware routing algorithm for networks-on-chip

Y Luo, MC Meyer, X Jiang… - 2019 IEEE 13th …, 2019 - ieeexplore.ieee.org
The Networks-on-Chip (NoC) is widely accepted as an advanced on-chip system which
replaces the traditional bus structure. NoC is promising as a solution for future many-core …

Runtime contention and bandwidth-aware adaptive routing selection strategies for networks-on-chip

FA Samman, T Hollstein… - IEEE Transactions on …, 2012 - ieeexplore.ieee.org
This paper presents adaptive routing selection strategies suitable for network-on-chip (NoC).
The main prototype presented in this paper uses contention information and bandwidth …

A new congestion-aware routing algorithm in network-on-chip: 2D and 3D comparison

K Gaffour, MK Benhaoua, AH Benyamina… - International Journal of …, 2023 - Taylor & Francis
Network on-Chip (NoC) is scalable, flexible, modular communication structure for Multi/Many-
core architectures. It allows simpler interconnect models with higher bandwidth compared to …