Impact of underfill fillet geometry on interfacial delamination in organic flip chip packages

K Kacker, S Sidharth, A Dubey… - 56th Electronic …, 2006 - ieeexplore.ieee.org
Underfill delamination jeopardy in flip chip organic packages is driven by shear and peeling
interfacial stresses, which are directly impacted by underfill fillet geometry. Finite element …

A simulation method for predicting packaging mechanical reliability with low/spl kappa/dielectrics

L Mercado, C Goldberg, SM Kuo - Proceedings of the IEEE …, 2002 - ieeexplore.ieee.org
It is essential to understand the impact of packaging on chips with copper/low k structures. In
this paper, a multi-level, multi-scale modeling technique is used to study the die attach …

Cracking failures in lead-on-chip packages induced by chip backside contamination

M Aamagi, H Seno, K Ebe, R Baumann… - 1994 Proceedings …, 1994 - ieeexplore.ieee.org
The increasingly severe demands of concurrently increasing die size while reducing
package size have made the mechanical stability of novel surface mount technologies a …

Micro structure observation and reliability behavior of peripheral flip chip interconnections with solder-capped Cu pillar bumps

Y Orii, K Toriyama, S Kohara, H Noma… - Transactions of The …, 2011 - jstage.jst.go.jp
Abstract PoP (Package on Package) structures have been used widely in digital consumer
electronics products such as digital still cameras and mobile phones. However, the final …

The effect of underfill imperfections on the reliability of flip chip modules: FEM simulations and experiments

S Rzepka, F Feustel, E Meusel… - … Conference (Cat. No …, 1998 - ieeexplore.ieee.org
The stresses occurring in the solder joints during thermal cyclic loads have been assessed
by finite element analysis and experimental tests in order to study the effect of hidden …

Temperature effect of interfacial fracture toughness on underfill for Pb-free flip chip packages

S Park, Z Tang, S Chung - 2007 Proceedings 57th Electronic …, 2007 - ieeexplore.ieee.org
In this study, the interfacial fracture toughness between passivation layer and underfill was
investigated at elevated temperatures by performing conventional four-point bending test …

Modeling of flip-chip underfill delamination and cracking with five input manufacturing variables

Y Yang, MK Toure, PM Souare, E Duchesne… - Microelectronics …, 2022 - Elsevier
The chip corner geometry and the mismatch of the coefficient of thermal expansion cause a
local stress concentration in the underfill near the chip corner area. Delamination at the chip …

CuBOL (Cu-column on BOL) technology: A low cost flip chip solution scalable to high I/O density, fine bump pitch and advanced Si-nodes

S Movva, S Bezuk, O Bchir, M Shah… - 2011 IEEE 61st …, 2011 - ieeexplore.ieee.org
An innovative packaging solution-Cu-column on BOL'(CuBOL) is developed that
dramatically reduces flip chip package cost and offers superior product reliability, thus …

[图书][B] Chip package interaction (CPI) and its impact on the reliability of flip-chip packages

X Zhang - 2009 - search.proquest.com
Chip-package interaction (CPI) has become a critical reliability issue for flip-chip packaging
of Cu/low-k chip with organic substrate. The thermo-mechanical deformation and stress …

Mechanisms of die and underfill cracking in flip chip PBGA package

JB Shim, EC Ahn, TJ Cho, HJ Moon… - … and Interfaces (Cat …, 2000 - ieeexplore.ieee.org
This paper focuses on understanding the mechanisms of die and underfill cracking during
MRT (Moisture Resistance Test, JEDEC level 3) and TCT (Thermal Cycling Test,-55-125/spl …