Reliability of fine-pitch flip-chip packages
B Banijamali, I Mohammed… - 2009 59th Electronic …, 2009 - ieeexplore.ieee.org
A new low-cost flip-chip technology that leverages the existing fine pitch flip-chip
technologies is discussed. For decades, the C4 process has served as the main …
technologies is discussed. For decades, the C4 process has served as the main …
Thermal fatigue reliability for Cu-Pillar bump interconnection in flip chip on module and underfill effects
JB Kwak, S Chung - Soldering & Surface Mount Technology, 2015 - emerald.com
Purpose–The purpose of this paper is to assess the thermo-mechanical reliability of a solder
bump with different underfills, with the evaluation of different underfill materials. As there is …
bump with different underfills, with the evaluation of different underfill materials. As there is …
Fab Integrated Packaging (FIP): a new concept for high reliability wafer-level chip size packaging
M Topper, J Auersperg, V Glaw… - … Conference (Cat. No …, 2000 - ieeexplore.ieee.org
Wafer Level Packaging has the highest potential for future single chip packages. The
package is completed directly on the wafer then singulated by dicing for the assembly in a …
package is completed directly on the wafer then singulated by dicing for the assembly in a …
Effect of material and geometry parameters on the thermo-mechanical reliability of flip-chip assemblies
S Michaelides, SK Sitaraman - ITherm'98. Sixth Intersociety …, 1998 - ieeexplore.ieee.org
Detailed models have been created to understand the effect of material and geometry
parameters on die stresses and solder bump strains in flip-chip assemblies. The following …
parameters on die stresses and solder bump strains in flip-chip assemblies. The following …
Adhesion study on underfill encapsulant affected by flip chip assembly variables
L Fan, KS Moon, CP Wong - … International Symposium on …, 2001 - ieeexplore.ieee.org
Underfill material is a polymeric adhesive which is used in flip chip devices. It encapsulates
the solder joints by filling the gap between silicon die and organic substrate. Within a typical …
the solder joints by filling the gap between silicon die and organic substrate. Within a typical …
Interfacial Fracture Analysis of CMOS Cu/Low- BEOL Interconnect in Advanced Packaging Structures
CC Lee, CC Chiu, CC Hsia… - IEEE Transactions on …, 2009 - ieeexplore.ieee.org
The increasing use of Cu/low-k dielectrics as multilevel interconnect inclusion materials and
aggressive scaling in advanced back-end of line (BEOL) results in a considerable challenge …
aggressive scaling in advanced back-end of line (BEOL) results in a considerable challenge …
Interface reliability assessments for copper/low-k products
CD Hartfield, ET Ogawa, YJ Park… - IEEE Transactions on …, 2004 - ieeexplore.ieee.org
Multiple new materials are being adopted by the semiconductor industry at a rapid rate for
both semiconductor devices and packages. These advances are driving significant …
both semiconductor devices and packages. These advances are driving significant …
Copper die bumps (first level interconnect) and low-K dielectrics in 65nm high volume manufacturing
A Yeoh, M Chang, C Pelto, TL Huang… - 56th Electronic …, 2006 - ieeexplore.ieee.org
The benefits of copper (Cu) die-side bumps for flip chip application are well known and have
been sought for more than a decade. However, the introduction of fragile low-k interlayer …
been sought for more than a decade. However, the introduction of fragile low-k interlayer …
Chip-package interaction: Challenges and solutions to mechanical stability of Back end of Line at 28nm node and beyond for advanced flip chip application
F Kuechenmeister, D Breuer, H Geisler… - 2012 IEEE 14th …, 2012 - ieeexplore.ieee.org
Fhis paper discusses the extensive development work carried out by GLOBALFOUNDRIES
to mitigate chip-package interaction (CPI) risks for the silicon Backend of Line (BEOL) during …
to mitigate chip-package interaction (CPI) risks for the silicon Backend of Line (BEOL) during …