22.1 a 90gs/s 8b 667mw 64× interleaved sar adc in 32nm digital soi cmos
Forthcoming optical communication standards such as ITU OTU-4 and 100/400Gb/s
Ethernet require ADCs with more than 50GS/s and at least 5 ENOB to enable complex …
Ethernet require ADCs with more than 50GS/s and at least 5 ENOB to enable complex …
An 11b 3.6 GS/s time-interleaved SAR ADC in 65nm CMOS
Over the last years several low-power time-interleaved (TI) ADC designs in the 2.5-to-3.0
GS/s range have been published [1-3], intended for integration in applications like radar …
GS/s range have been published [1-3], intended for integration in applications like radar …
11.2 A 0.85 fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS
HY Tai, YS Hu, HW Chen… - 2014 IEEE International …, 2014 - ieeexplore.ieee.org
Analog-to-digital converters (ADC) are extensively used in wireless sensor networks and
healthcare electronic devices to monitor long-term signal conditions. It is essential to prolong …
healthcare electronic devices to monitor long-term signal conditions. It is essential to prolong …
A 35mW8 b 8.8 GS/s SAR ADC with low-power capacitive reference buffers in 32nm Digital SOI CMOS
An asynchronous 8× interleaved redundant SAR ADC achieving 8.8 GS/s at 35mW and 1V
supply is presented. The ADC features pass-gate selection clocking scheme for time-skew …
supply is presented. The ADC features pass-gate selection clocking scheme for time-skew …
A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS
An 8 b SAR ADC is presented. The 90 nm CMOS prototype achieves an ENOB of 7.8 b at a
sampling frequency of 10.24 MS/S. The use of asynchronous dynamic CMOS logic, custom …
sampling frequency of 10.24 MS/S. The use of asynchronous dynamic CMOS logic, custom …
A 5-GS/s 10-b 76-mW time-interleaved SAR ADC in 28 nm CMOS
J Fang, S Thirunakkarasu, X Yu… - … on Circuits and …, 2017 - ieeexplore.ieee.org
This paper presents a 5-GS/s 12-way 10-b time-interleaved successive approximation
register (SAR) ADC for direct sampling receivers. Proper signal and clock distribution along …
register (SAR) ADC for direct sampling receivers. Proper signal and clock distribution along …
A 10-Bit 5 MS/s VCO-SAR ADC in 0.18- m CMOS
This brief presents a 10-bit 5 MS/s hybrid analog-to-digital converter (ADC) combining
successive approximation register (SAR) with voltage-controlled oscillator (VCO) in 0.18-μm …
successive approximation register (SAR) with voltage-controlled oscillator (VCO) in 0.18-μm …
A 4.2 mw 50 ms/s 13 bit CMOS SAR ADC with SNR and SFDR enhancement techniques
T Miki, T Morie, K Matsukawa, Y Bando… - IEEE Journal of Solid …, 2015 - ieeexplore.ieee.org
This paper presents a SAR ADC with 71 dB SNDR and 85 dB SFDR at 50 MS/s while
keeping low power consumption of 4.2 mW. To achieve high resolution without large …
keeping low power consumption of 4.2 mW. To achieve high resolution without large …
26.5 A 5.5 mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS
Communication devices such as 60GHz-band receivers and serial links demand power-
efficient low-resolution gigahertz-sampling-rate ADCs. However, the energy efficiency of …
efficient low-resolution gigahertz-sampling-rate ADCs. However, the energy efficiency of …
A 32 mW 1.25 GS/s 6b 2b/Step SAR ADC in 0.13m CMOS
Z Cao, S Yan, Y Li - IEEE journal of solid-state circuits, 2009 - ieeexplore.ieee.org
A 1.25 GS/s 6b ADC is implemented in a 0.13 mum digital CMOS process by time-
interleaving two SAR ADCs with 2.5 GHz internal clock frequency that converts 6 bits in 3 …
interleaving two SAR ADCs with 2.5 GHz internal clock frequency that converts 6 bits in 3 …