Hardened design based on advanced orthogonal Latin code against two adjacent multiple bit upsets (MBUs) in memories

L Xiao, J Li, J Li, J Guo - Sixteenth international symposium on …, 2015 - ieeexplore.ieee.org
Soft errors have been a concern in memory reliability for many years. With device feature
size decreasing and memories density increasing, a single event upset (SEU) in memory …

Implementing triple adjacent error correction in double error correction orthogonal Latin squares codes

P Reviriego, S Liu, JA Maestro, S Lee… - … on Defect and Fault …, 2013 - ieeexplore.ieee.org
Soft errors have been a concern in memories for many years. In older technologies, soft
errors typically affected a single memory cell but as technology scaled, Multiple Cell Upsets …

A method to extend orthogonal Latin square codes

P Reviriego, S Pontarelli… - … Transactions on very …, 2013 - ieeexplore.ieee.org
Error correction codes (ECCs) are commonly used to protect memories from errors. As
multibit errors become more frequent, single error correction codes are not enough and …

Two bit overlap: a class of double error correction one step majority logic decodable codes

P Reviriego, S Liu, O Rottenstreich… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
Error Correction Codes (ECCs) are commonly used to protect memories against soft errors
with an impact on memory area and delay. For large memories, the area overhead is mostly …

Extend orthogonal Latin square codes for 32-bit data protection in memory applications

S Liu, L Xiao, Z Mao - Microelectronics Reliability, 2016 - Elsevier
As CMOS technology size scales down, multiple cell upsets (MCUs) caused by a single
radiation particle have become one of the most challenging reliability issues for memories …

[PDF][PDF] Efficient error detection in double error correction orthogonal latin squares codes

P Reviriego, SF Liu, S Lee… - Second workshop on …, 2013 - median-project.eu
Reliability is a major concern in advanced electronic circuits. Errors caused for example by
radiation become more common as technology scales. To ensure that those errors do not …

Reducing the cost of triple adjacent error correction in double error correction orthogonal latin square codes

S Liu, P Reviriego, L Xiao… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
As multiple cell upsets (MCUs) become more frequent on SRAM memory devices, there is a
growing interest on error correction codes that can correct multibit errors. Orthogonal Latin …

A (64, 45) triple error correction code for memory applications

P Reviriego, M Flanagan… - IEEE Transactions on …, 2011 - ieeexplore.ieee.org
Memories are commonly protected with error correction codes to avoid data corruption when
a soft error occurs. Traditionally, per-word single error correction (SEC) codes are used. This …

Concurrent error detection for orthogonal Latin squares encoders and syndrome computation

P Reviriego, S Pontarelli… - IEEE transactions on very …, 2012 - ieeexplore.ieee.org
Error correction codes (ECCs) are commonly used to protect memories against errors.
Among ECCs, orthogonal latin squares (OLS) codes have gained renewed interest for …

A scheme to reduce the number of parity check bits in orthogonal Latin square codes

P Reviriego, S Liu, A Sánchez-Macián… - IEEE Transactions …, 2017 - ieeexplore.ieee.org
The use of error-correcting codes is a common strategy to protect memories from errors.
Single-error correction, double-error detection linear block codes have been traditionally …