In response to the growing gap between memory access time and processor speed, DRAM
manufacturers have created several new DRAM architectures. This paper presents a …

This paper presents a simulation-based performance study of several of the new high-
performance DRAM architectures, each evaluated in a small system organization. These …

Given a fixed CPU architecture and a fixed DRAM timing specification, there is still a large
design space for a DRAM system organization. Parameters include the number of memory …

To feed the high degrees of parallelism in modern graphics processors and manycore CPU
designs, DRAM manufacturers have created new DRAM architectures that deliver high …

DRAM has been a de facto standard for main memory, and advances in process technology
have led to a rapid increase in its capacity and bandwidth. In contrast, its random access …

In this paper we address the severe performance gap caused by high processor clock rates
and slow DRAM accesses. We show that even with an aggressive, next-generation memory …

In current systems, memory accesses to a DRAM chip must obey a set of minimum latency
restrictions specified in the DRAM standard. Such timing parameters exist to guarantee …

DRAM has been the dominant technology for architecting main memory for decades. Recent
trends in multi-core system design and large-dataset applications have amplified the role of …

Contemporary DRAM systems have maintained impressive scaling by managing a careful
balance between performance, power, and storage density. In achieving these goals, a …

The widespread use of multicore processors has dramatically increased the demand on
high memory bandwidth and large memory capacity. As DRAM subsystem designs stretch to …