In this paper, we present a new fully adaptive routing algorithm for partially interconnected
cross-link mesh topology for NoC named as partially interconnected fully adaptive routing …

Development of a new regular topology for Network on Chip (NoC) is a challenging task, as
the proposed design should meet the application specific targets of latency, throughput …

The existing System on Chip (SoC) design will soon become a critical bottle neck in chip
performance with its inability to scale its communication network effectively with decreasing …

With the rapid development of semiconductor industry, the number of cores integrated on
chip increases quickly, which brings tough challenges such as bandwidth, scalability and …

Network-on-Chips (NoC) has been proven as a flexible solution for Chip-Multiprocessor
(CMP) systems due to its reusability and scalability. To increase communication efficiency …

Network-on-Chip (NoC) has emerged as a long-term and efficient on-chip communication
solution for MCSoC and CMP micro-architectures to overcome bottleneck of traditional bus …

Network-on-Chip (NoC) is thought to be an effective packet-switched on chip arrangement
for System-on-Chip (SoC) paradigm. Using router in a NoC, higher throughput is facilitated …

Routing algorithm has a significant impact on the overall performance of network-on-chip
(NoC) based system due to the unbalanced nature of NoC traffic. In this paper, we propose …

3D die stacking integration technology offers a feasible and promising solution to overcome
the barriers of interconnect efficiency and device scaling in modern systems. The emerging …

Abstract Network-on-Chip (NoC) has proven itself as a viable alternative for the on-chip
communication among processing cores in recent years. In Diametrical 2D Mesh …