Vector computation unit in a neural network processor

GM Thorson, CA Clark, D Luu - US Patent 10,074,051, 2018 - Google Patents
A circuit for performing neural network computations for a neural network comprising a
plurality of layers, the circuit comprising: activation circuitry configured to receive a vector of …

Neural network processor

J Ross, NP Jouppi, AE Phelps, RC Young… - US Patent …, 2017 - Google Patents
A circuit for performing neural network computations for a neural network comprising a
plurality of neural network layers, the circuit comprising: a matrix computation unit configured …

Neural network processor

J Ross, NP Jouppi, AE Phelps, RC Young… - US Patent …, 2020 - Google Patents
A circuit for performing neural network computations for a neural network comprising a
plurality of neural network layers, the circuit comprising: a matrix computation unit configured …

Neural network processor

J Ross, NP Jouppi, AE Phelps, RC Young… - US Patent …, 2017 - Google Patents
(57) ABSTRACT A circuit for performing neural network computations for a neural network
comprising a plurality of neural network layers, the circuit comprising: a matrix computation …

Neural network processor

KH Lee, S Ravikumar, P Donnelly… - US Patent App. 16 …, 2020 - Google Patents
A circuit for performing computations for a neural network comprising multiple neural
network (NN) layers. The circuit includes a processing device that provides programming …

Pipelined hardware implementation of a neural network circuit

CB McBride - US Patent 6,836,767, 2004 - Google Patents
According to a first aspect of the invention, a pipelined hardware implementation of a neural
network circuit is provided. The inventive neural network circuit includes an input Stage for …

Prefetching weights for use in a neural network processor

J Ross - US Patent 10,049,322, 2018 - Google Patents
A circuit for performing neural network computations for a neural network, the circuit
comprising: a systolic array comprising a plurality of cells; a weight fetcher unit configured to …

Hardware node having a mixed-signal matrix vector unit

DC Burger - US Patent 10,860,924, 2020 - Google Patents
Processors and methods for neural network processing are provided. A method in a
processor including a matrix vector unit is provided. The method includes receiving vector …

Hardware node having a matrix vector unit with block-floating point processing

ES Chung, DC Burger, D Lo, K Ovtcharov - US Patent 10,167,800, 2019 - Google Patents
Processors and methods for neural network processing are provided. A method includes
receiving vector data corre sponding to a layer of a neural network model, where each of the …

Neural network processor configurable using macro instructions

JW Brothers, J Lee - US Patent 11,244,225, 2022 - Google Patents
Implementing a neural network can include receiving a macro instruction for implementing
the neural network within a control unit of a neural network processor. The macro instruction …