57) ABSTRACT A timing generator which is capable of generating a timing Signal with high
resolution and accuracy which is not affected by the changes in temperature and power …

(57) ABSTRACT A signal generating circuit for generating a delayed signal in response to a
pulsed timing signal with a delay time which is not substantially affected by variations in …

ABSTRACT OF THE DISCLOSURE A solid-state timing circuit which is capable of ac
curately timing a relatively long interval. The circuit uses a field-effect transistor which has its …

An internal clock signal generating circuit includes a selector, a delay line, a 2-frequency
divider, a phase comparator and a shift register. The selector alternately selects an external …

A timing generating device, in which a period genera tor generates pulses the average
period of which is equal to a preset period, at intervals of an integral of a reference clock …

A timing adjustment circuit consists of a delay circuit made from n delay elements (n is an
integer of 2 or more) connected in series, with which an input signal p0 is delayed in …

57 ABSTRACT A timing signal generating circuit including a clock source which generates
clock pulses of a predetermined period, a binary counter which divides the frequency of the …

Flled: Sep'1'1999 When a reset signal (PLL-RST) is input, an arithmetic unit (30) Foreign
Application Priority Data(12) measures the cycle of an input clock (IN) With a pulse counter …

A control transistor is connected in parallel with an input transistor of a bias generation
circuit in a voltage control delay circuit. A power supply potential Vcc is divided by voltage …

In view of the foregoing, it is an object of the present invention to provide a clock signal
supplying circuit in which a clock skew between a clock signal passed through a path for …