Roc: Dram-based processing with reduced operation cycles

X Xin, Y Zhang, J Yang - Proceedings of the 56th Annual Design …, 2019 - dl.acm.org
DRAM based memory-centric computing architectures are promising solutions to tackle the
challenges of memory wall. In this paper, we develop a novel design of DRAM-based …

Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture

A Olgun, F Bostanci… - ACM Transactions on …, 2024 - dl.acm.org
Modern computing systems access data in main memory at coarse granularity (eg, at 512-bit
cache block granularity). Coarse-grained access leads to wasted energy because the …

Dramdig: A knowledge-assisted tool to uncover dram address mapping

M Wang, Z Zhang, Y Cheng… - 2020 57th ACM/IEEE …, 2020 - ieeexplore.ieee.org
As recently emerged rowhammer exploits require undocumented DRAM address mapping,
we propose a generic knowledge-assisted tool, DRAMDig, which takes domain knowledge …

A case for memory content-based detection and mitigation of data-dependent failures in DRAM

S Khan, C Wilkerson, D Lee… - IEEE Computer …, 2016 - ieeexplore.ieee.org
DRAM cells in close proximity can fail depending on the data content in neighboring cells.
These failures are called data-dependent failures. Detecting and mitigating these failures …

Cooldram: An energy-efficient and robust dram

N Rohbani, MA Soleimani… - 2023 IEEE/ACM …, 2023 - ieeexplore.ieee.org
DRAM is the most mature and widely-utilized memory structure as main memory in
computing systems. However, energy dissipation and latency of DRAM are two of the most …

Strong, thorough, and efficient memory protection against existing and emerging DRAM errors

J Kim - 2016 - repositories.lib.utexas.edu
Memory protection is necessary to ensure the correctness of data in the presence of
unavoidable faults. As such, large-scale systems typically employ Error Correcting Codes …

Mitigating wordline crosstalk using adaptive trees of counters

SM Seyedzadeh, AK Jones… - 2018 ACM/IEEE 45th …, 2018 - ieeexplore.ieee.org
DRAM technology scaling has the undesirable side effect of degrading cell reliability. One
such concern of deeply scaled DRAMs is the increased coupling between adjacent cells …

Learning to mitigate rowhammer attacks

BK Joardar, TK Bletsch… - 2022 Design, Automation …, 2022 - ieeexplore.ieee.org
Rowhammer is a vulnerability that arises due to the undesirable interaction between
physically adjacent rows in DRAMs. Existing DRAM protections are not adequate to defend …

PULSAR: Simultaneous many-row activation for reliable and high-performance computing in off-the-shelf DRAM chips

IE Yuksel, YC Tugrul, F Bostanci, AG Yaglikci… - arXiv preprint arXiv …, 2023 - arxiv.org
Data movement between the processor and the main memory is a first-order obstacle
against improving performance and energy efficiency in modern systems. To address this …

Enabling the adoption of processing-in-memory: Challenges, mechanisms, future research directions

S Ghose, K Hsieh, A Boroumand… - arXiv preprint arXiv …, 2018 - arxiv.org
Poor DRAM technology scaling over the course of many years has caused DRAM-based
main memory to increasingly become a larger system bottleneck. A major reason for the …