Survey of low power testing of VLSI circuits
P Basker, A Arulmurugan - 2012 International Conference on …, 2012 - ieeexplore.ieee.org
The System-On-Chip (SoC) revolution challenges both design and test engineers,
especially in the area of power dissipation. Generally, a circuit or system consumes more …
especially in the area of power dissipation. Generally, a circuit or system consumes more …
Low power testing of VLSI circuits: Problems and solutions
P Girard - … IEEE 2000 First International Symposium on Quality …, 2000 - ieeexplore.ieee.org
Power and energy consumption of digital systems may increase significantly during testing.
This extra power consumption due to test application may give rise to severe hazards to the …
This extra power consumption due to test application may give rise to severe hazards to the …
Test power: a big issue in large SOC designs
Y Bonhomme, P Girard, C Landrault… - … on Electronic Design …, 2002 - ieeexplore.ieee.org
Test power relates to the power consumed during test of integrated circuits or embedded
cores. Test power is now a big concern in large System-on-Chip designs. In this work, we …
cores. Test power is now a big concern in large System-on-Chip designs. In this work, we …
Test of low power circuits: Issues and industrial practices
Managing the power consumption of circuits and systems is challenging not only during
functional operations but also during manufacturing test. This paper discusses industrial …
functional operations but also during manufacturing test. This paper discusses industrial …
Why and how controlling power consumption during test: a survey
Managing the power consumption of circuits and systems is challenging not only during
functional operations but also during manufacturing test. In this paper, we first explain why it …
functional operations but also during manufacturing test. In this paper, we first explain why it …
Survey of low-power testing of VLSI circuits
P Girard - IEEE Design & test of computers, 2002 - ieeexplore.ieee.org
The author reviews low-power testing techniques for VLSI circuits. He prefaces this with a
discussion of power consumption that gives reasons for and consequences of increased …
discussion of power consumption that gives reasons for and consequences of increased …
Impact of SoC power management techniques on verification and testing
B Kapoor, S Hemmady, S Verma, K Roy… - … on Quality Electronic …, 2009 - ieeexplore.ieee.org
We are at the crossroads of some fundamental changes that are taking place in the
semiconductor industry. Power is a primary design criterion for bulk of the semiconductor …
semiconductor industry. Power is a primary design criterion for bulk of the semiconductor …
Suitability of Various Low‐Power Testing Techniques for IP Core‐Based SoC: A Survey
U Mehta, K Dasgupta, N Devashrayee - VLSI Design, 2011 - Wiley Online Library
Test power is the major issue for current generation VLSI testing. It has become the biggest
concern for today′ s SoC. While reducing the design efforts, the modular design approach …
concern for today′ s SoC. While reducing the design efforts, the modular design approach …
Test scheduling for minimal energy consumption under power constraints
T Schuele, AP Stroele - … 19th IEEE VLSI Test Symposium. VTS …, 2001 - ieeexplore.ieee.org
Power consumption has become a crucial concern in built-in self-test (BIST) due to the
increased switching activity in the circuit under test. In this paper we present a method for …
increased switching activity in the circuit under test. In this paper we present a method for …
Testing for SoCs with advanced static and dynamic power-management capabilities
X Kavousianos, K Chakrabarty - … & Test in Europe Conference & …, 2013 - ieeexplore.ieee.org
Many multicore chips today employ advanced power management techniques. Multi-
threshold CMOS (MTCMOS) is very effective for reducing standby leakage power. Dynamic …
threshold CMOS (MTCMOS) is very effective for reducing standby leakage power. Dynamic …