(57) ABSTRACT A processor has an instruction fetch unit that fetches ISA instructions from
memory and execution units that perform operations on instruction operands to generate …

(57) ABSTRACT A processor includes a front-end portion that issues instruc-tions to
execution units that execute the issued instructions. A hardware neural network unit (NNU) …

A processor comprising a mode indicator, a plurality of processing cores, and a neural
network unit (NNU), comprising a memory array, an array of neural processing units (NPU) …

The present disclosure relates to a processor for implement ing artificial neural networks, for
example, convolutional neural networks. The processor includes a memory control ler …

A processor comprises a neural network unit (NNU) and a processing complex (PC)
comprising a processing core and cache memory. The NNU comprises neural processing …

A processor comprising a plurality of processing cores, a last level cache memory (LLC)
shared by the plurality of processing cores, and a neural network unit (NNU) comprising an …

At least one neural network accelerator performs operations of a first subset of layers of a
neural network on an input data set, generates an intermediate data set, and stores the inter …

A processing unit for neural network processing includes: an instruction memory that stores
tasks including one or more instructions; a data memory that stores data related to the tasks; …

(57) ABSTRACT A deep neural network (“DNN”) module compresses and decompresses
neuron-generated activation data to reduce the utilization of memory bus bandwidth. The …

A neural network unit (NNU) includes N neural processing units (NPU). Each NPU has an
arithmetic unit and an accumulator. First and second multiplexed registers of the N NPUs …