Power consumption of very large scale integrated (VLSI) systems is much higher during
testing as a result of increased circuit activity. This paper presents a novel low-power D flip …

In this paper, a new scan flip-flop is proposed for low power testing. Different flip-flops
(Master-slave, hybrid, pulse triggered) are reviewed and evaluated their performance using …

Power consumption in scan based testing is high due to the toggling of the combinational
logic during the scan shift. In this paper, we present a modified Scan Flip-flop architecture …

Power dissipation in digital systems may be significantly high during scan testing where a
large portion of power is consumed in the combinational part. This paper presents a new …

This paper proposes a low power scan test scheme and formulates a problem based on this
scheme. In this scheme the flip-flops are grouped into N scan chains. At any time, only one …

The power consumption of modern highly complex chips during scan test is significantly
higher than the power consumed during functional mode. This leads to substantial heat …

We present a novel scan architecture for simultaneously reducing test application time and
test power (both average and peak power). Unlike previous works where the scan chain is …

This paper presents a novel toggle-masking technique that eliminates the switching activity
in a circuit under test (CUT) during the scan-shifting in a test-per-scan test. Conventional …

Excessive switching activity in test mode results in higher power dissipation than normal
mode of operation and becoming a serious issue, in order to avoid reliability problems …

It is seen that power dissipation during test mode is quite high compared to that during the
functional mode of operation of a digital circuit. This may lead to damage of certain chips …