Low-power testing for low-power devices
X Wen - 2010 IEEE 25th International Symposium on Defect …, 2010 - ieeexplore.ieee.org
Low-power devices are indispensable for modern electronic applications, and numerous
hardware/software techniques have been developed for drastically reducing functional …
hardware/software techniques have been developed for drastically reducing functional …
Modified scan flip-flop for low power testing
A Mishra, N Sinha, V Singh… - 2010 19th IEEE …, 2010 - ieeexplore.ieee.org
Scanning of test vectors during testing causes unnecessary and excessive switching in the
combinational circuit compared to that in the normal operation. In this paper, we propose a …
combinational circuit compared to that in the normal operation. In this paper, we propose a …
A gated clock scheme for low power scan testing of logic ICs or embedded cores
Y Bonhomme, P Girard, L Guiller… - … 10th Asian Test …, 2001 - ieeexplore.ieee.org
Test power is now a big concern in large system-on-chip designs. In this paper, we present a
novel approach for minimizing power consumption during scan testing of integrated circuits …
novel approach for minimizing power consumption during scan testing of integrated circuits …
Reductions of instantaneous power by ripple scan clocking
K Joshi, E MacDonald - 23rd IEEE VLSI Test Symposium (VTS' …, 2005 - ieeexplore.ieee.org
The exponential increase in the number of transistors implemented in integrated circuits in
each new generation of CMOS technology is causing an explosion not only in functional …
each new generation of CMOS technology is causing an explosion not only in functional …
Tutorial T3A: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices
S Ravi, V Chickermane… - 2014 27th International …, 2014 - ieeexplore.ieee.org
Summary form only given, as follows. The push for portable, battery-operated, and “cool-and-
green” electronics has elevated power consumption as the defining metric of integrated …
green” electronics has elevated power consumption as the defining metric of integrated …
Controlling peak power during scan testing
R Sankaralingam, NA Touba - Proceedings 20th IEEE VLSI …, 2002 - ieeexplore.ieee.org
This paper presents a procedure for modifying a given set of scan vectors so that the peak
power during scan testing is kept below a specified limit without reducing fault coverage …
power during scan testing is kept below a specified limit without reducing fault coverage …
Survey of low power testing of VLSI circuits
P Basker, A Arulmurugan - 2012 International Conference on …, 2012 - ieeexplore.ieee.org
The System-On-Chip (SoC) revolution challenges both design and test engineers,
especially in the area of power dissipation. Generally, a circuit or system consumes more …
especially in the area of power dissipation. Generally, a circuit or system consumes more …
Low power testing of VLSI circuits: Problems and solutions
P Girard - … IEEE 2000 First International Symposium on Quality …, 2000 - ieeexplore.ieee.org
Power and energy consumption of digital systems may increase significantly during testing.
This extra power consumption due to test application may give rise to severe hazards to the …
This extra power consumption due to test application may give rise to severe hazards to the …
On low-capture-power test generation for scan testing
X Wen, Y Yamashita, S Kajihara… - 23rd IEEE VLSI Test …, 2005 - ieeexplore.ieee.org
Research on low-power scan testing has been focused on the shift mode, with little or no
consideration given to the capture mode power. However, high switching activity when …
consideration given to the capture mode power. However, high switching activity when …
Why and how controlling power consumption during test: a survey
Managing the power consumption of circuits and systems is challenging not only during
functional operations but also during manufacturing test. In this paper, we first explain why it …
functional operations but also during manufacturing test. In this paper, we first explain why it …