This work presents the modeling of the impact of elevated temperatures on the SET
occurrence and their characteristics in an IBM 65-nm Bulk CMOS technology. The …

The single event transients (SETs) are a common source of malfunction in nano-scale
CMOS integrated circuits. For this reason, evaluation of the SET effects and application of …

Single event transients (SETs) stand out as one of the major causes of soft errors in
nanoscale CMOS integrated circuits. To reduce the need for exhaustive circuit simulations in …

This paper presents a SET predictive methodology based on coupled MUSCA SEP3 and
electrical simulations (CADENCE tool). The method is validated by SET measurements on …

Abstract Analysis of Single Event Transient (SET) effects is an important step in the design of
radiation-hardened integrated circuits for space missions. Because the simulation of SET …

With the downscaling of CMOS technologies, the radiation-induced Single Event Transient
(SET) effects in combinational logic have become a critical reliability issue for modern …

SET propagation and mitigation in 65-nm CMOS test structures are investigated. Radiation
tests showed a clear distortion of the SET pulse-widths related to the structures' design and …

This work presents an efficient hybrid simulation approach, developed for accurate
characterization of single-event transients (SETs) in combinational logic. Using this …

Radiation-induced single-event transients (SETs) are the leading cause of mal-operations in
CMOS nanometric integrated circuits. The increasing complexity of advanced CMOS digital …

L'augmentation de la densité et la réduction de la tension d'alimentation des circuits intégrés
rend la contribution des effets singuliers induits par les radiations majoritaire dans la …