Error floor investigation and girth optimization for certain types of low-density parity check codes
L Sun, H Song, BVKV Kumar - Proceedings.(ICASSP'05). IEEE …, 2005 - ieeexplore.ieee.org
Low-density parity check (LDPC) codes with their near-Shannon capacity limit error
correcting performance and iterative decoding algorithm are being evaluated for digital …
correcting performance and iterative decoding algorithm are being evaluated for digital …
FPGA based implementation of decoder for array low-density parity-check codes
Low density parity check (LDPC) codes have received much attention for their excellent
performance, and the inherent parallelism involved in decoding them. We consider a type of …
performance, and the inherent parallelism involved in decoding them. We consider a type of …
Programmable LDPC decoder based on the bubble-sort algorithm
R Singhal, G Choi… - … Conference on VLSI …, 2006 - ieeexplore.ieee.org
Low density parity check (LDPC) codes are one of the most powerful error correcting codes
known. Recent research have pointed out their potential for a low cost, low latency hardware …
known. Recent research have pointed out their potential for a low cost, low latency hardware …
A serial concatenated scheme for LDPC code to achieve better error correction performance
Z Wang, M Zhang - 2012 2nd International Conference on …, 2012 - ieeexplore.ieee.org
Low Density Parity Check (LDPC) Codes is a class of approaching limits error correction
codes which has gained widely application in communications. The excellent performance …
codes which has gained widely application in communications. The excellent performance …
A class of efficient-encoding generalized low-density parity-check codes
In this paper, we investigate an efficient encoding approach for generalized low-density
(GLD) parity check codes, a generalization of Gallager's (1962, 1963) low-density parity …
(GLD) parity check codes, a generalization of Gallager's (1962, 1963) low-density parity …
Parallel LDPC decoding on a network-on-chip based multiprocessor platform
WH Hu, JH Bahn… - 2009 21st International …, 2009 - ieeexplore.ieee.org
Low Density Parity Check (LDPC) code is an error correction code that can achieve
performance close to Shannon limit and inherently suitable for parallel implementation. It …
performance close to Shannon limit and inherently suitable for parallel implementation. It …
Code design and decoder implementation of low density parity check code
MK Ku, HS Li, YH Chien - Conference, Emerging Information …, 2005 - ieeexplore.ieee.org
Low-density parity-check (LDPC) codes have been widely considered as error-correcting
codes for next generation communication systems. A good LDPC decoder design requires …
codes for next generation communication systems. A good LDPC decoder design requires …
An FPGA implementation of low-density parity-check code decoder with multi-rate capability
With superior error correction capability, low-density parity-check (LDPC) has initiated wide
scale interests in wireless telecommunication fields. In the past, various structures of single …
scale interests in wireless telecommunication fields. In the past, various structures of single …
Configurable, high throughput, irregular LDPC decoder architecture: Tradeoff analysis and implementation
M Karkooti, P Radosavljevic… - IEEE 17th International …, 2006 - ieeexplore.ieee.org
Low Density Parity Check (LDPC) codes are one of the best error correcting codes that
enable the future generations of wireless devices to achieve higher data rates. This paper …
enable the future generations of wireless devices to achieve higher data rates. This paper …
Bit flipping-sum product algorithm for regular LDPC codes
R El Alami, CB Gueye, M Boussetta… - … Symposium On I/V …, 2010 - ieeexplore.ieee.org
In this paper we present Low Density Parity Check decoding algorithm that assemble two
different algorithms: Sum-Product and Bit-Flipping; we denote Bit Flipping-Sum Product …
different algorithms: Sum-Product and Bit-Flipping; we denote Bit Flipping-Sum Product …