Sleep transistors are effective to reduce dynamic and leakage power. The cluster-based
design was proposed to reduce the sleep transistor area by clustering gates to minimize the …

Power Gating is effective for reducing leakage power. Previously, a Distributed Sleep
Transistor Network (DSTN) was proposed to reduce the sleep transistor area by connecting …

Optimum power gating sleep transistor design and implementation are critical to a
successful low-power design. This paper describes important considerations for the sleep …

Optimum sleep transistor design and implementation are critical to a successful power-
gating design. This paper describes a number of critical considerations for the sleep …

Multithreshold CMOS (MTCMOS) technology has become a popular technique for standby
power reduction. Sleep transistor insertion in circuits is an effective application of MTCMOS …

Power gating is a circuit technique that enables high performance and low power operation.
One of the challenges in power gating is sizing the sleep transistor which is used to gate the …

Multi-threshold CMOS is a popular circuit style that will provide high performance and low
power operation. Optimally sizing the gating sleep transistor to provide adequate …

Reducing power dissipation is one of the most principle subjects in VLSI design today.
Scaling causes subthreshold leakage currents to become a large component of total power …

Multi-threshold CMOS is an increasingly popular circuitapproach that enables high
performance and low power operation. However, no methodologies have been developed …

Multithreshold CMOS (MTCMOS) circuits reduce standby leakage power with low delay
overhead. Most MTCMOS designs cut off the power to large blocks of logic using large sleep …