SyLVaaS: System level formal verification as a service

T Mancini, F Mari, A Massini, I Melatti… - Fundamenta …, 2016 - content.iospress.com
Abstract The goal of System Level Formal Verification is to show system correctness
notwithstanding uncontrollable events (disturbances), as for example faults, variations in …

System level validation using formal techniques

R Drechsler, D Große - IEE Proceedings-computers and digital techniques, 2005 - IET
Owing to increasing design complexity and intensive reuse of components, verifying the
correctness of circuits and systems becomes a more and more important factor. In the …

System level formal verification via distributed multi-core hardware in the loop simulation

T Mancini, F Mari, A Massini, I Melatti… - 2014 22nd Euromicro …, 2014 - ieeexplore.ieee.org
The goal of System Level Formal Verification (SLFV) is to show system correctness
notwithstanding uncontrollable events (such as: faults, variation in system parameters …

Oeritte: User-friendly counterexample explanation for model checking

P Ovsiannikova, I Buzhinsky, A Pakonen… - IEEE Access, 2021 - ieeexplore.ieee.org
Thorough verification is a part of the design process of instrumentation and control systems if
they must comply with crucial safety requirements. Model checking can be applied to the …

Model checking of safety-critical software in the nuclear engineering domain

J Lahtinen, J Valkonen, K Björkman, J Frits… - Reliability Engineering & …, 2012 - Elsevier
Instrumentation and control (I&C) systems play a vital role in the operation of safety-critical
processes. Digital programmable logic controllers (PLC) enable sophisticated control tasks …

VeriAgent: an approach to integrating UML and formal verification tools

E Mota, E Clarke, A Groce, W Oliveira, M Falcao… - Electronic notes in …, 2004 - Elsevier
The mathematical notations of Formal Verification Tools (FVTs) do not prevent us from
wrongly defining the behavior of systems, any more than modern CASE tools do. With …

[PDF][PDF] Practical applications of model checking in the Finnish nuclear industry

A Pakonen, T Tahvonen, M Hartikainen… - … Topical Meeting on …, 2017 - researchgate.net
Model checking is a powerful, formal, computer-assisted verification method that can be
used to prove that a model of a (hardware or software) system fulfills stated properties. When …

[PDF][PDF] Constructing checkers from PSL properties

SV Gheorghita, R Grigore - … Conference on Control Systems and Computer …, 2005 - Citeseer
Model checking and simulation are the main techniques widely used in hardware
verification. The past years trend is to bring together these two verification techniques in …

Temporal logic model checking

E Clarke, A Fehnker, SK Jha, H Veith - Handbook of Networked and …, 2005 - Springer
Errors in safety-critical systems such as embedded controllers may have drastic
consequences and can even endanger human life. It is therefore crucially important to verify …

Formal verification of safety PLC based control software

D Darvas, I Majzik, E Blanco Viñuela - … 2016, Reykjavik, Iceland, June 1-5 …, 2016 - Springer
Abstract Programmable Logic Controllers (PLCs) are widely used in the industry for various
industrial automation tasks. Besides non-safety applications, the usage of PLCs became …