A 24-GHz fully integrated integer-N phase-locked loop (PLL) is presented in this paper.
Benefiting from the bias noise filtering technique, the voltage controlled oscillator (VCO) in …

The feasibility of low noise sensitivity 2.4-GHz Phase Locked Loop for use in wireless
communications as well as in clock generation circuit is demonstrated. The system uses low …

A 1.2 V 60 GHz 120 mW phase-locked loop employing a quadrature differential voltage-
controlled oscillator, a programmable charge pump, and a frequency quadrupler is …

An X-band 9.75/10.6 GHz fully-integrated low-power consumption phase-locked loop (PLL)
is designed and fabricated on standard 0.18-μm CMOS process. Through the band control …

A phase-locked loop front-end including a LC voltage controlled oscillator and an IQ
injection locked frequency divider is presented. The operation ranges of the VCO and ILFD …

Implemented in a standard 0.18-mum CMOS process, a 0.5-V 1.9-GHz low-power phase-
locked loop (PLL) is presented. Due to the use of the forward-body-bias technique, the …

This paper presents a fully-integrated 5.5 GHz low-power consumption phase-locked loop
(PLL) on standard 0.18-µm CMOS process. Utilizing the transformer feedback VCO and high …

The design and experimental verification of a 75-GHz phase-locked loop (PLL) fabricated in
90-nm CMOS technology is presented. The circuit incorporates a three-quarter wavelength …

In this paper, a 64.3–66.2 GHz digitally calibrated phase-locked loop (PLL) is presented in
0.13 μm CMOS technology. A digital calibration circuit is adopted to align the center …

A low power and low phase noise phase-locked loop (PLL) is proposed in this paper to
provide a quadrature millimeter-wave source for the 60GHz direct-conversion transceiver …