A switchable PLL frequency synthesizer and hot carrier effects

Y Liu, A Srivastava, Y Xu - Proceedings of the 19th ACM Great Lakes …, 2009 - dl.acm.org
In this paper, a new strategy of switchable CMOS phase-locked loop frequency synthesizer
is proposed, designed and fabricated in 0.5 μm n-well CMOS process. Cadence/Spectre …

A low jitter 0.3-165 MHz CMOS PLL frequency synthesizer for 3 V/5 V operation

HC Yang, LK Lee, RS Co - IEEE Journal of Solid-State Circuits, 1997 - ieeexplore.ieee.org
This paper describes a phase-locked loop (PLL) based frequency synthesizer. The voltage-
controlled oscillator (VCO) utilizing a ring of single-ended current-steering amplifiers (CSA) …

A multi-band single-loop PLL frequency synthesizer with dynamically-controlled switched tuning VCO

AM Samuel, JP de Gyvez - … on Circuits and Systems (Cat. No …, 2000 - ieeexplore.ieee.org
A phase-locked loop (PLL) frequency synthesizer architecture for multiple-band applications
is presented. A dynamically-controlled switched tuning voltage-controlled oscillator (VCO) is …

Design and modelling of a low phase noise PLL frequency synthesizer

X He, W Kong, R Newcomb… - 2006 8th International …, 2006 - ieeexplore.ieee.org
This paper focuses on the low VCO sensitivity gain design, and modeling of a low phase
noise 2.4 GHz PLL frequency synthesizer. Tuning switch array is used in the LC tank to …

CMOS phase-locked loop circuits and hot carrier effects

Y Liu, A Srivastava - Journal of Low Power Electronics, 2012 - ingentaconnect.com
Three CMOS phase-locked loop (PLL) integrated circuits are designed in 0.5 μmn-well
CMOS process using single-ended voltage-controlled oscillator, differential voltage …

Low noise frequency synthesizer with self-calibrated voltage controlled oscillator and accurate AFC algorithm

P Qin, J Li, J Kang, X Li, J Zhou - Journal of semiconductors, 2014 - iopscience.iop.org
A low noise phase locked loop (PLL) frequency synthesizer implemented in 65 nm CMOS
technology is introduced. A VCO noise reduction method suited for short channel design is …

A VCO with high supply noise rejection and its application to PLL frequency synthesizer

T Sun, C Hui, Y Wang - IEEE International Symposium on …, 2005 - ieeexplore.ieee.org
A CMOS voltage-controlled oscillator (VCO) with high supply noise rejection is designed,
and its application to a phase-locked loop (PLL) frequency synthesizer is also presented. In …

A 20-GHz VCO for PLL synthesizer in 0.13-μm BiCMOS

J He, J Li, D Hou, YZ Xiong, DL Yan… - … on Radio-Frequency …, 2012 - ieeexplore.ieee.org
A 20-GHz voltage-controlled oscillator (VCO) for phase-locked loop (PLL) synthesizer is
presented in this paper. The VCO and PLL synthesizer have been implemented using only …

A PFD and Charge Pump switching circuit to optimize the output phase noise of the PLL in 0.13-µm CMOS

MK Hati, TK Bhattacharyya - 2015 International Conference on …, 2015 - ieeexplore.ieee.org
This paper presents the design of a novel Phase Frequency Detector (PFD) and Charge
Pump (CP) switching circuits for the frequency synthesizer in phase-locked loop (PLL). Our …

A low jitter 5.3-GHz 0.18-/spl mu/m CMOS PLL based frequency synthesizer

S Ali, F Jain - 2002 IEEE Radio Frequency Integrated Circuits …, 2002 - ieeexplore.ieee.org
A 5.3-GHz CMOS phase locked loop (PLL) based frequency synthesizer is reported. The
PLL operates as an integer-N frequency synthesizer using a ring-type voltage controlled …