In the case of field programmable gate array (FPGA) chips, as the demand for higher speeds
and enhanced functionality increases, the size of the flip chip die grows accordingly to offer …

Fan-out chip on substrate (FOCoS) is defined as the fan-out package flip-chip mounts on
high pin counts ball grid array substrate. 12-inch advanced wafer level package (aWLP) …

The need for thin core substrates is increasing in the industry to meet low inductance.
However, there are major challenges of reducing thin core substrate warpage in assembly …

The trend toward finer pitch and higher performance integrated circuits (ICs) devices has
driven the semiconductor industry to incorporate copper and low-k dielectric materials …

The low-k materials have intrinsically lower modulus and poorer adhesion compared to the
commonly used dielectric materials. Thus, thermo-mechanical failure is one of the major …

Chip-package-interaction (CPI) induced BEoL (back-end-of-line) delamination has emerged
as a major reliability concern with the adoption of Cu/low-k as the mainstream BEoL …

Coefficient of thermal expansion (CTE) mismatch between chip and substrate is the root
cause for reliability issues in flip chip packages, such as excessive warpage, low-k dielectric …

Warpage of organic flip chip ball grid array (FCBGA) package during IR-reflow results from
mismatch of componential coefficient of thermal expansion (CTE). It is distinctly affected by …

In recent years, the IoT popularity pushes the package development of 3C products into a
more functional and thinner target. For high I/O density and low cost considered package …

As Cu bump is widely adopted in microelectronic IC product packages for broader scope of
applications throughout network communication and handheld device, it impacts on the …