For constnicting large-scale shared-memory multi-processors, researchers are currently
exploring cache coherence protocols that do not rely on broadcast, but instead send …

To make shared-memory multiprocessors scalable, researchers are now exploring cache
coherence protocols that do not rely on broadcast, but instead send invalidation messages …

Write-invalidate and write-broadcast coherency protocols have been criticized for being
unable to achieve good bus performance across all cache configurations. In particular, write …

Parallel programs that use critical sections and are executed on a shared-memory
multiprocessor with a write-invalidate protocol result in invalidation actions that could be …

Parallel programs exhibit a small number of distinct data-sharing patterns. A common data-
sharing pattern, migratory access, is characterized by exclusive read and write access by …

The performance of the data cache in shared-memory multiprocessors has been shown to
be different from that in uniprocessors. In particular, cache miss rates in multiprocessors do …

Due to data spreading among processors and due to the cache coherence problem, private
data caches have not been as effective in reducing the average memory delay in …

Write-invalidate protocols suffer from memory-access penalties due to coherence misses.
While write-update or hybrid update/invalidate protocols can reduce coherence misses, the …

Improving performance and scalability in shared-memory multiprocessors requires an
appropriate solution to the well-known cache coherence problem. Hardware schemehighly …

Snooping and directory-based coherence protocols have become the de facto standard in
chip multi-processors, but neither design is without drawbacks. Snooping protocols are not …