Gate sizing and replication to minimize the effects of virtual ground parasitic resistances in MTCMOS designs

C Hwang, C Kang, M Pedram - 7th International Symposium on …, 2006 - ieeexplore.ieee.org
The Multi-Threshold CMOS (MTCMOS) technique can significantly reduce sub-threshold
leakage currents during the circuit sleep (standby) mode by adding high-V/sub th/power …

Sizing and placement of charge recycling transistors in MTCMOS circuits

E Pakbaznia, M Pedram, F Fallah - 2007 IEEE/ACM …, 2007 - ieeexplore.ieee.org
A downside of using Multi-Threshold CMOS (MTCMOS) technique for leakage reduction is
the energy consumption during transitions between sleep and active modes. Previously, a …

Functionality directed clustering for low power MTCMOS design

TW Chang, TT Hwang, SY Hsu - Proceedings of the 2005 Asia and …, 2005 - dl.acm.org
Multi-Threshold CMOS (MTCMOS) is a circuit style that can effectively reduce leakage
power consumption. Sleep transistor sizing is the key issue when MTCMOS circuit is …

Fast techniques for standby leakage reduction in MTCMOS circuits

W Wang, M Anis, S Areibi - IEEE International SOC Conference …, 2004 - ieeexplore.ieee.org
Technology scaling causes subthreshold leakage currents to increase exponentially.
Therefore, effective leakage minimization techniques must be designed. In addition, for a …

Ground bouncing noise suppression techniques for MTCMOS circuits

H Jiao, V Kursun - 2009 1st Asia Symposium on Quality …, 2009 - ieeexplore.ieee.org
Ground bouncing noise produced during the sleep to active mode transitions is an important
challenge in multithreshold CMOS (MTCMOS) circuits. The effectiveness of different noise …

Sleep transistor distribution in row-based MTCMOS designs

C Hwang, P Rong, M Pedram - Proceedings of the 17th ACM Great …, 2007 - dl.acm.org
The Multi-Threshold CMOS (MTCMOS) technology has become a popular technique for
standby power reduction. This technology utilizes high-Vth sleep transistors to reduce sub …

Transistor sizing issues and tool for multi-threshold CMOS technology

J Kao, A Chandrakasan, D Antoniadis - Proceedings of the 34th annual …, 1997 - dl.acm.org
Multi-threshold CMOS is an increasingly popular circuitapproach that enables high
performance and low power operation. However, no methodologies have been developed …

OFF stage leakage analysis from Power Gating application in deep sub-micron technology

LK Yong - 2009 1st Asia Symposium on Quality Electronic …, 2009 - ieeexplore.ieee.org
It is ubiquitous that high performance integrated circuits designs are commonly suffers from
total chip power consumption. Moreover, when we are marching towards deeper sub-micron …

An auto-backgate-controlled MT-CMOS circuit

H Makino, Y Tsujihashi, K Nii… - 1998 Symposium on …, 1998 - ieeexplore.ieee.org
As various portable systems get popular, the reduction of the power dissipation in LSIs is
becoming more essential. The scaling down of both the supply voltage and threshold …

Charge recycling between virtual power and ground lines for low energy MTCMOS

Z Liu, V Kursun - … on Quality Electronic Design (ISQED'07), 2007 - ieeexplore.ieee.org
Multi-threshold voltage CMOS (MTCMOS) has emerged as an increasingly popular
technique for reducing the leakage energy consumption of idle circuits. The MTCMOS …