RF characterization and modelling of high density through silicon vias for 3D chip stacking

L Cadix, C Bermond, C Fuchs, A Farcy, P Leduc… - Microelectronic …, 2010 - Elsevier
3D integration including Through Silicon Vias is more and more considered as the solution
to overcome conventional 2D IC issues. In this way, TSV analytical equivalent models are …

Integration and frequency dependent parametric modeling of Through Silicon Via involved in high density 3D chip stacking

L Cadix, C Fuchs, M Rousseau, P Leduc… - ECS …, 2010 - iopscience.iop.org
Evaluation of Through Silicon Via (TSV) electrical performance is hardly required today to
improve heterogeneous 3D chip performance in the frame of a “more than Moore” approach …

RF characterization and analytical modelling of through silicon vias and coplanar waveguides for 3D integration

YPR Lamy, KB Jinesh, F Roozeboom… - IEEE Transactions …, 2010 - ieeexplore.ieee.org
High-aspect ratio (12.5) through silicon vias (TSV) made in a silicon interposer have been
electrically characterized in the direct current (dc) and microwave regimes for 3D …

Integration and frequency dependent electrical modeling of Through Silicon Vias (TSV) for high density 3DICs

L Cadix, M Rousseau, C Fuchs, P Leduc… - 2010 IEEE …, 2010 - ieeexplore.ieee.org
Evaluation of Through Silicon Via (TSV) electrical parameters is mandatory to improve
heterogeneous 3D chip performance in the frame of a “more than Moore” roadmap. Accurate …

An efficient and simple compact modeling approach for 3-D interconnects with IC׳ s stack global electrical context consideration

JE Lorival, F Calmon, F Sun, F Frantz, C Plossu… - Microelectronics …, 2015 - Elsevier
Abstract 3D integration is considered to be the most promising solution to overcome
challenges encountered currently in planar technologies. As an emerging technology …

High frequency characterization and modeling of high density TSV in 3D integrated circuits

C Bermond, L Cadix, A Farcy… - … IEEE Workshop on …, 2009 - ieeexplore.ieee.org
High frequency characterization and modeling of Through Silicon Vias (TSVs) for new 3D
chip staking are presented in this paper. Works focus on high density TSVs, up to 10 6 cm-2 …

Analytical modeling and analysis of through silicon vias (TSVs) in high speed three-dimensional system integration

MA Ehsan, Z Zhou, Y Yi - Progress In Electromagnetics Research M, 2015 - jpier.org
This paper gives a comprehensive study on the modeling and design challenges of Through
Silicon Vias (TSVs) in high speed three dimensional (3D) system integration. To investigate …

Rigorous electrical modeling of through silicon vias (TSVs) with MOS capacitance effects

T Bandyopadhyay, KJ Han, D Chung… - IEEE Transactions …, 2011 - ieeexplore.ieee.org
3-D integration of microelectronic systems reduces the interconnect length, wiring delay, and
system size, while enhancing functionality by heterogeneous integration. Through silicon via …

Integration challenges of copper through silicon via (TSV) metallization for 3D-stacked IC integration

J Van Olmen, C Huyghebaert, J Coenen… - Microelectronic …, 2011 - Elsevier
In this paper we will highlight key integration issues that were encountered during the
development of the 3D-stacked IC Through Silicon Via (TSV) module and present solutions …

Electrical modeling and characterization of through silicon via for three-dimensional ICs

G Katti, M Stucchi, K De Meyer… - IEEE transactions on …, 2009 - ieeexplore.ieee.org
Three-dimensional ICs provide a promising option to build high-performance compact SoCs
by stacking one or more chips vertically. Through silicon vias (TSVs) form an integral …