Optimizing energy efficiency of 3-D multicore systems with stacked DRAM under power and thermal constraints

J Meng, K Kawakami, AK Coskun - Proceedings of the 49th Annual …, 2012 - dl.acm.org
3D multicore systems with stacked DRAM have the potential to boost system performance
significantly; however, this performance increase may cause 3D systems to exceed the …

Temperature aware thread migration in 3D architecture with stacked DRAM

D Zhao, H Homayoun… - … Symposium on Quality …, 2013 - ieeexplore.ieee.org
A 3D architecture with DRAM memory stacked on a multi-core processor has many benefits
for the embedded system. Compared with a conventional 2D design, it reduces memory …

Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy

GH Loh - Proceedings of the 42nd Annual IEEE/ACM …, 2009 - dl.acm.org
3D-integration is a promising technology to help combat the" Memory Wall" in future multi-
core processors. Past work has considered using 3D-stacked DRAM as a large last-level …

3D DRAM design and application to 3D multicore systems

H Sun, J Liu, RS Anigundi, N Zheng… - IEEE Design & Test …, 2009 - ieeexplore.ieee.org
Editor's note: From a system architecture perspective, 3D technology can satisfy the high
memory bandwidth demands that future multicore/manycore architectures require. This …

Simultaneous multi-layer access: Improving 3D-stacked memory bandwidth at low cost

D Lee, S Ghose, G Pekhimenko, S Khan… - ACM Transactions on …, 2016 - dl.acm.org
3D-stacked DRAM alleviates the limited memory bandwidth bottleneck that exists in modern
systems by leveraging through silicon vias (TSVs) to deliver higher external memory …

An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth

DH Woo, NH Seong, DL Lewis… - HPCA-16 2010 The …, 2010 - ieeexplore.ieee.org
Memory bandwidth has become a major performance bottleneck as more and more cores
are integrated onto a single die, demanding more and more data from the system memory …

3D-stacked memory architectures for multi-core processors

GH Loh - ACM SIGARCH computer architecture news, 2008 - dl.acm.org
Three-dimensional integration enables stacking memory directly on top of a microprocessor,
thereby significantly reducing wire delay between the two. Previous studies have examined …

PPT: joint performance/power/thermal management of DRAM memory for multi-core systems

CH Lin, CL Yang, KJ King - Proceedings of the 2009 ACM/IEEE …, 2009 - dl.acm.org
With the popularity of multi-core architecture, to sustain the memory demands from different
cores, the memory system is expected to grow significantly in both speed and capacity. This …

Dynamic thermal management in 3D multicore architectures

AK Coskun, JL Ayala, D Atienza… - … , Automation & Test …, 2009 - ieeexplore.ieee.org
Technology scaling has caused the feature sizes to shrink continuously, whereas
interconnects, unlike transistors, have not followed the same trend. Designing 3D stack …

System-level power/performance evaluation of 3D stacked DRAMs for mobile applications

M Facchini, T Carlson, A Vignon… - … , Automation & Test …, 2009 - ieeexplore.ieee.org
Convergence of communication, consumer applications and computing within mobile
systems pushes memory requirements both in terms of size, bandwidth and power …