With the current trend toward multicore architectures, improved execution performance can
no longer be obtained via traditional single-thread instruction level parallelism (ILP), but …

Efficiently utilizing multicore processors to improve their performance potentials demands
extracting thread-level parallelism from the applications. Various novel and sophisticated …

Thread-Level Speculation (TLS) facilitates the extraction of parallel threads from sequential
applications. Most prior work has focused on developing the compiler and architecture for …

This paper presents the Mitosis framework, which is a combined hardware-software
approach to speculative multithreading, even in the presence of frequent dependences …

Threads experiencing long-latency loads on a simultaneous multith-reading (SMT)
processor may clog shared processor resources without making forward progress, thereby …

Thread-level parallelism (TLP) has been extensively studied in order to overcome the
limitations of exploiting instruction-level parallelism (ILP) on high-performance superscalar …

Speculative multithreading (SpMT) is a thread-level automatic parallelization technique,
which partitions sequential programs into multithreads to be executed in parallel. This paper …

The traditional single-core processors are being replaced by chip multiprocessors (CMPs)
where several processor cores are integrated on a single chip. While this is beneficial for …

As multi-core architectures with Thread-Level Speculation (TLS) are becoming better
understood, it is important to focus on TLS compilation. TLS compilers are interesting in that …

General-purpose computing is taking an irreversible step toward on-chip parallel
architectures. One way to enhance the performance of chip multiprocessors is the use of …