Built-in self test of S2I switched current circuits
GE Sether, C Toumazou, G Taylor, K Eckersall… - … Integrated Circuits and …, 1996 - Springer
This article presents a new concept for built-in self test of switched current circuits based on
S 2 I memory cells. From the spectrum of possible transistor defects reported in CMOS …
S 2 I memory cells. From the spectrum of possible transistor defects reported in CMOS …
A concurrent error detection IC in 2-/spl mu/m static CMOS logic
JC Lo, SY Sun, JC Daly - IEEE journal of solid-state circuits, 1994 - ieeexplore.ieee.org
When a comprehensive fault model is considered, static CMOS VLSI has long been
prohibited from realizing concurrent error detecting (CED) circuits due to the unique analog …
prohibited from realizing concurrent error detecting (CED) circuits due to the unique analog …
[PDF][PDF] IDDQ testing of low voltage CMOS operational transconductance amplifier
M Kaur, J Kaur - International Journal of …, 2018 - download.garuda.kemdikbud.go.id
The paper describes the design for testability (DFT) of low voltage two stage operational
transconductance amplifiers based on quiescent power supply current (IDDQ) testing. IDDQ …
transconductance amplifiers based on quiescent power supply current (IDDQ) testing. IDDQ …
Design for testability techniques for CMOS combinational gates
G Buonanno, F Lombardi, D Sciuto… - IEEE transactions on …, 1991 - ieeexplore.ieee.org
The design of easily testable CMOS combinational circuits is discussed. Two CMOS
structured design techniques are presented. The novelty of this approach is the complete …
structured design techniques are presented. The novelty of this approach is the complete …
Design of CMOS circuits for stuck-open fault testability
AP Jayasumana, YK Malaiya… - IEEE journal of solid …, 1991 - ieeexplore.ieee.org
A CMOS design that offers highly testable CMOS circuits is presented. The design requires a
minimal amount of extra hardware for testing. The test phase for the proposed design is …
minimal amount of extra hardware for testing. The test phase for the proposed design is …
[图书][B] Defect oriented testing for CMOS analog and digital circuits
M Sachdev - 2013 - books.google.com
Defect oriented testing is expected to play a significant role in coming generations of
technology. Smaller feature sizes and larger die sizes will make ICs more sensitive to …
technology. Smaller feature sizes and larger die sizes will make ICs more sensitive to …
[引用][C] Testing stuck-on faults in CMOS integrated circuits
YK Malaiya - Proc. Int. Conf. Computer-Aided Design, 1984
Design rules for CMOS self checking circuits with parametric faults in the functional block
C Metra, M Favalli, P Olivo… - Proceedings of 1993 IEEE …, 1993 - ieeexplore.ieee.org
The authors investigate the detection of parametric bridging and delay faults in the functional
block of self checking circuits (SCCS). As far as these faults are concerned, classical …
block of self checking circuits (SCCS). As far as these faults are concerned, classical …
Design for testability of embedded integrated operational amplifiers
K Arabi, B Kaminska - IEEE Journal of Solid-State Circuits, 1998 - ieeexplore.ieee.org
The operational amplifier (op amp) is one of the most encountered analog building blocks. In
this paper, the problem of testing an integrated op amp is treated. A new low-cost vectorless …
this paper, the problem of testing an integrated op amp is treated. A new low-cost vectorless …