A technique is proposed for implementing BIST (built-in self-test) in a CMOS arithmetic and
logic unit (ALU). The approach covers single stuck-open faults and all functional faults that …

We present the results of hardware experiments designed to determine the relative
contribution of CMOS coupling mechanisms to off-path signal variations caused by common …

In the last few years CMOS technology has become increas ingly dominant for realizing Very
Large Scale Integrated (VLSI) circuits. The popularity of this technology is due to its high den …

The last step in the development of a BIST structure employing a new self-test technique for
analog circuits is presented in this paper, namely the design and implementation of a …

A testable CMOS design technique in which some extra transistors are used in such a way
that the CMOS gate is converted to a pseudo-nMOS/pMOS gate during testing is discussed …

A push-pull current circuit for biasing CMOS amplifiers with rail-to-rail input common-mode
range is presented. By means of a feedback action, the circuit avoids the large magnitude …

A complete data retention test of a CMOS SRAM array accomplished at room temperature
using the soft-defect detection (SDD) technique is reported. The SDD technique uses a …

This paper investigates the detection of parametric bridging and delay faults affecting the
functional block of CMOS self-checking circuits (SCCs). As far as these faults are concerned …

A strategy for testing for data retention faults in CMOS static random access memories
(SRAMs) is proposed. Sensing the voltage at one of the data bus lines with a proper design …

A previous realization of a fault tolerant architecture at CMOS level, while guaranteeing the
correct behavior of the circuit both in the fault-free situation and in the presence of stuck-on …