A previous realization of a fault tolerant architecture at CMOS level, while guaranteeing the
correct behavior of the circuit both in the fault-free situation and in the presence of stuck-on …

An SEM based system for a complete characterization of latch‐up in CMOS integrated circuits
Page 1 SCANNING Vol. 8, 20-33 (1986) 0 FACM, Inc. Received: October 11, 1985 Original …

A new class AB CMOS operational amplifier (opamp) principle is presented. It is based on a
novel self-biasing input transistor technique. The operational transconductance amplifier …

In this paper, a simple behavior-level fault model, which is able to represent the faulty
behavior of the closed-loop operational amplifier (OP), is presented. The fault model …

The technique of monitoring the RMS value of the AC component of the supply current of an
analogue integrated circuit has been shown to be very effective at detecting hard faults. A …

A method for design of built-in testable (BIT) error detection and correction (EDAC) circuits is
presented that uses up to 65% less test hardware than customary BIT implementations. A 1 …

A design technique which facilitates testing for stuck-open faults in CMOS VLSI circuits with
scan paths is described. In this technique, the combinational circuitry is implemented with …

The most difficult fault category in electronic systems is the “No Fault Found”(NFF). It is
considered to be the most costly fault category in, for instance, avionics. The relatively few …

Although many integrated circuit processing or in-field defects change the functional
behaviour of the circuit and may be detected by classical testing techniques, small spot and …

Defect models have been used for testability analysis of BiCMOS circuits and the results
have been compared with an analysis of CMOS circuits. Using a nominal point approach …