A review of low-power static random access memory (sram) designs

N Rathi, A Kumar, N Gupta… - 2023 IEEE Devices for …, 2023 - ieeexplore.ieee.org
The growing demand for low-power static random access memory (SRAM) cells in Internet
of Things (IoT) devices has led to the development of various SRAM cell topologies that …

A single ended 6T SRAM cell design for ultra-low-voltage applications

J Singh, DK Pradhan, S Hollis… - IEICE Electronics …, 2008 - jstage.jst.go.jp
In this paper, we present a novel six-transistor (6T) single-ended static random access
memory (SE-SRAM) cell for ultralow-voltage applications. The proposed design has a strong …

A Schmitt-trigger based low read power 12T SRAM cell

A Sachdeva, VK Tomar - Analog integrated circuits and signal processing, 2020 - Springer
In this article, a Schmitt trigger based 12-Transistors (ST12T) static random-access memory
(SRAM) bit-cell has been proposed. The Read Power of proposed cell is reduced by …

[PDF][PDF] Design and simulation of 6T SRAM cell architectures in 32nm technology

G Apostolidis, D Balobas, N Konofaos - Journal of Engineering Science and …, 2016 - jestr.org
A comparative study of various 6T SRAM cell layouts is presented at 32 nm, including four
symmetric topologies. The comparison comprises two conventional cells, a thin cell, which is …

Low-power and high speed SRAM for ultra low power applications

N Meshram, G Prasad, D Sharma… - 2022 IEEE International …, 2022 - ieeexplore.ieee.org
The rapid development of battery-powered gadgets has made low-power design a priority in
recent years. In addition, integrated SRAM units in contemporary soCs have become an …

Design and analysis of area and power optimised SRAM cell for high-speed processor

G Prasad, B chandra Mandi… - 2020 First International …, 2020 - ieeexplore.ieee.org
The basic 6T Static random access memory (SRAM) cell experience from relatively high
static and total power loss problem, to solve this 8T, NC cells were designed. But this all …

Analyzing the Performance of 6T SRAM Cell and 64× 64 Memory Array at Lower Technology Nodes for Low Power Design

T Singh, V Prakash, SS Anwer… - 2023 1st International …, 2023 - ieeexplore.ieee.org
SRAM plays an important role in achieving high computational speed in digital systems. Its
fast access times, low latency, random access, and high reliability make it an essential …

[PDF][PDF] 8T SRAM cell design for dynamic and leakage power reduction

M Gopal, DSS Prasad, B Raj - International Journal of Computer …, 2013 - researchgate.net
This paper addresses a, novel eight transistor (8T) CMOS SRAM cell design to enhance the
stability and to reduce dynamic and leakage power. We compared our results with reported …

Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes

Y Morita, H Fujiwara, H Noguchi, Y Iguchi… - IEICE transactions on …, 2007 - search.ieice.org
This paper shows that an 8T SRAM cell is superior to a 6T cell in terms of cell area in a
future process. At a 65-nm node and later, the 6T cell comprised of the minimum-channel …

[PDF][PDF] A Novel Architecture of SRAM Cell Using Single Bit-Line

G Kalaiarasi, V Indhumaraghathavalli… - International Journal of … - researchgate.net
Low power 6T SRAM cell can be used for different purposes including embedded
applications and stand alone applications. Many circuit techniques for active and standby …