As multiple cell upsets (MCUs) become more frequent on SRAM memory devices, there is a
growing interest on error correction codes that can correct multibit errors. Orthogonal Latin …

The use of error-correcting codes is a common strategy to protect memories from errors.
Single-error correction, double-error detection linear block codes have been traditionally …

In recent years, there has been a growing interest in multi-bit error correction codes (ECCs)
to protect SRAM memories. This has been caused by the increased number of multiple …

There has been recent interest on designing double error correction (DEC) codes for 32-bit
data words that support fast decoding as they can be useful to protect memories. To that …

Soft errors have been a concern in memories for many years. In older technologies, soft
errors typically affected a single memory cell but as technology scaled, Multiple Cell Upsets …

Error correction codes (ECCs) are commonly used to protect memories against errors.
Among ECCs, orthogonal latin squares (OLS) codes have gained renewed interest for …

The dominant errors for memories with multilevel cells are due to interference and low data
retention which causes the threshold voltage to shift compared to its original value. Thus, the …

Soft errors have been a concern in memory reliability for many years. With device feature
size decreasing and memories density increasing, a single event upset (SEU) in memory …

Error correction codes (ECCs) are commonly used to protect memories from errors. As
multibit errors become more frequent, single error correction codes are not enough and …

Static random access memories (SRAMs) are key in electronic systems. They are used not
only as standalone devices, but also embedded in application specific integrated circuits …