Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy

GH Loh - Proceedings of the 42nd Annual IEEE/ACM …, 2009 - dl.acm.org
3D-integration is a promising technology to help combat the" Memory Wall" in future multi-
core processors. Past work has considered using 3D-stacked DRAM as a large last-level …

3D-stacked memory architectures for multi-core processors

GH Loh - ACM SIGARCH computer architecture news, 2008 - dl.acm.org
Three-dimensional integration enables stacking memory directly on top of a microprocessor,
thereby significantly reducing wire delay between the two. Previous studies have examined …

Near data processing: Impact and optimization of 3D memory system architecture on the uncore

SM Hassan, S Yalamanchili… - Proceedings of the 2015 …, 2015 - dl.acm.org
A promising recent development that can provide continued scaling of performance is the
ability to stack multiple DRAM layers on a multi-core processor die. This paper analyzes the …

ATCache: Reducing DRAM cache latency via a small SRAM tag cache

CC Huang, V Nagarajan - … of the 23rd international conference on …, 2014 - dl.acm.org
3D-stacking technology has enabled the option of embedding a large DRAM onto the
processor. Prior works have proposed to use this as a DRAM cache. Because of its large …

Design of 3D DRAM and its application in 3D integrated multi-core computing systems

H Sun, J Liu, R Anigundi, N Zheng, J Lu… - IEEE Design and …, 2009 - ieeexplore.ieee.org
This paper concerns appropriate 3D DRAM architecture design and the potential of using
3D DRAM to implement both L2 cache and main memory in 3D multi-core processor-DRAM …

An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth

DH Woo, NH Seong, DL Lewis… - HPCA-16 2010 The …, 2010 - ieeexplore.ieee.org
Memory bandwidth has become a major performance bottleneck as more and more cores
are integrated onto a single die, demanding more and more data from the system memory …

Simultaneous multi-layer access: Improving 3D-stacked memory bandwidth at low cost

D Lee, S Ghose, G Pekhimenko, S Khan… - ACM Transactions on …, 2016 - dl.acm.org
3D-stacked DRAM alleviates the limited memory bandwidth bottleneck that exists in modern
systems by leveraging through silicon vias (TSVs) to deliver higher external memory …

3D DRAM design and application to 3D multicore systems

H Sun, J Liu, RS Anigundi, N Zheng… - IEEE Design & Test …, 2009 - ieeexplore.ieee.org
Editor's note: From a system architecture perspective, 3D technology can satisfy the high
memory bandwidth demands that future multicore/manycore architectures require. This …

Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores

F Hameed, L Bauer, J Henkel - … & Test in Europe Conference & …, 2013 - ieeexplore.ieee.org
On-chip DRAM caches may alleviate the memory bandwidth problem in future multi-core
architectures through reducing off-chip accesses via increased cache capacity. For memory …

Decoupled fused cache: Fusing a decoupled LLC with a DRAM cache

E Vasilakis, V Papaefstathiou, P Trancoso… - ACM Transactions on …, 2019 - dl.acm.org
DRAM caches have shown excellent potential in capturing the spatial and temporal data
locality of applications capitalizing on advances of 3D-stacking technology; however, they …