A selective read-before-write scheme for energy-aware spin torque transfer RAM (STT-RAM) cache design
T Zhang, T Chen, J Wu, Y Qu - Journal of Circuits, Systems and …, 2013 - World Scientific
Due to its low leakage power and high density, spin torque transfer RAM (STT-RAM) has
become a good candidate for future on-chip cache. However, STT-RAM suffers from higher …
become a good candidate for future on-chip cache. However, STT-RAM suffers from higher …
Energy-efficient Spin-Transfer Torque RAM cache exploiting additional all-zero-data flags
Large on-chip caches account for a considerable fraction of the total energy consumption in
modern microprocessors. In this context, emerging Spin-Transfer Torque RAM (STT-RAM) …
modern microprocessors. In this context, emerging Spin-Transfer Torque RAM (STT-RAM) …
A data migration approach for L1 cache design with SRAM and volatile STT-RAM
WK Cheng, YH Ciou - Intelligent Systems and Applications, 2015 - ebooks.iospress.nl
Abstract Spin-Transfer Torque RAM (STT-RAM) has the advantages of circuit density and
ignorable leakage power. However, it suffers from the bad write latency and poor write …
ignorable leakage power. However, it suffers from the bad write latency and poor write …
Architecture and data migration methodology for L1 cache design with hybrid SRAM and volatile STT-RAM configuration
WK Cheng, YH Ciou, PY Shen - Microprocessors and Microsystems, 2016 - Elsevier
Abstract Spin-Transfer Torque RAM (STT-RAM) has the advantages of circuit density and
ignorable leakage power. However, it suffers from the bad write latency and poor write …
ignorable leakage power. However, it suffers from the bad write latency and poor write …
CWC: A companion write cache for energy-aware multi-level spin-transfer torque RAM cache design
T Zhang, J Zhu, J Fu, T Chen - Journal of Circuits, Systems and …, 2015 - World Scientific
Due to its large leakage power and low density, the conventional SARM becomes less
appealing to implement the large on-chip cache due to energy issue. Emerging non-volatile …
appealing to implement the large on-chip cache due to energy issue. Emerging non-volatile …
Lower-bits cache for low power STT-RAM caches
As power-efficient design becomes more important, spin-transfer torque RAM (STT-RAM)
has drawn a lot of attention due to its ability to meet both high performance and low power …
has drawn a lot of attention due to its ability to meet both high performance and low power …
Mirrorcache: An energy-efficient relaxed retention l1 sttram cache
K Kuan, T Adegbija - Proceedings of the 2019 on Great Lakes …, 2019 - dl.acm.org
Spin-Transfer Torque RAM (STTRAM) is a promising alternative to SRAMs in on-chip
caches, due to several advantages, including non-volatility, low leakage, high integration …
caches, due to several advantages, including non-volatility, low leakage, high integration …
An adjacent-line-merging writeback scheme for stt-ram-based last-level caches
Spin-Transfer Torque RAM (STT-RAM) has attracted attention as a key element for the Last-
Level Cache (LLC) of a future microprocessor. Since STT-RAM has a higher density than …
Level Cache (LLC) of a future microprocessor. Since STT-RAM has a higher density than …
Energy reduction for STT-RAM using early write termination
The emerging Spin Torque Transfer memory (STT-RAM) is a promising candidate for future
on-chip caches due to STT-RAM's high density, low leakage, long endurance and high …
on-chip caches due to STT-RAM's high density, low leakage, long endurance and high …
Compiler-assisted refresh minimization for volatile STT-RAM cache
Spin-transfer torque RAM (STT-RAM) has been proposed to build on-chip caches because
of its attractive features such as high storage density and ultra low leakage power. However …
of its attractive features such as high storage density and ultra low leakage power. However …